SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

• US 20120213000A1
• Filed: 02/09/2012
• Published: 08/23/2012
• Est. Priority Date: 02/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEMURA, Yasuhiko
• Granted Patent: US 8,975,680 B2
• Time in Patent Office: Days
• US Class Current: 365/174
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F² at a minimum.

Claims

1. A semiconductor memory device comprising a gain cell, the gain cell comprising:

a read bit line formed in or over a substrate;

a projecting insulator formed over the substrate;

a write word line that is formed on a side surface of the projecting insulator and faces with a gate insulator interposed therebetween;

a semiconductor interposed between the write word line and the side surface of the projecting insulator;

an electrode provided over a top of the projecting insulator; and

a write bit line that is provided over the projecting insulator and is electrically connected to the electrode.

2. The semiconductor memory device according to claim 1,

wherein a height of the projecting insulator is greater than or equal to 1 time and less than or equal to 20 times a distance between the projecting insulator and an adjacent projecting insulator.

3. The semiconductor memory device according to claim 1,

wherein a height of the write word line is greater than or equal to 30% and less than or equal to 90% of a height of the projecting insulator.

4. The semiconductor memory device according to any one of claim 1, further comprising a driver circuit below the read bit line.

5. The semiconductor memory device according to claim 1,

wherein a depth of the read bit line is different from a depth of another read bit line.

6. The semiconductor memory device according to claim 1,

wherein a layer in which a portion of the read bit line is formed is different from a layer in which a portion of another read bit line is formed.

7. The semiconductor memory device according to claim 1,

wherein the semiconductor includes a material whose band gap is greater than or equal to 2.5 eV and less than or equal to 4 eV.

8. The semiconductor memory device according to claim 1,

wherein the semiconductor includes an oxide semiconductor.

9. A semiconductor memory device comprising a gain cell, the gain cell comprising:

a read bit line formed in or over a substrate;

a first conductive layer;

a write word line that is formed over the first conductive layer;

a semiconductor in contact with the first conductive layer;

a first insulator interposed between the write word line and the semiconductor;

a second conductive layer provided over an upper portion of the semiconductor, the second conductive layer being in contact with the semiconductor;

a read word line that is formed on a side surface of the first conductive layer and faces with a second insulator interposed therebetween; and

a write bit line that is provided over the second conductive layer and is electrically connected to the second conductive layer.

10. The semiconductor memory device according to claim 9,

wherein the conductive layer functions a memory node of the gain cell.

11. The semiconductor memory device according to claim 9,

wherein the first insulator is the same material as the second insulator.

12. The semiconductor memory device according to claim 9, further comprising a driver circuit below the read bit line.

13. The semiconductor memory device according to claim 9,

wherein a depth of the read bit line is different from a depth of another read bit line.

14. The semiconductor memory device according to claim 9,

wherein a layer in which a portion of the read bit line is formed is different from a layer in which a portion of another read bit line is formed.

15. The semiconductor memory device according to claim 9,

wherein the semiconductor includes a material whose band gap is greater than or equal to 2.5 eV and less than or equal to 4 eV.

16. The semiconductor memory device according to claim 9,

wherein the semiconductor includes an oxide semiconductor.

17. A method of manufacturing a semiconductor memory device comprising a gain cell, comprising the steps of:

forming a read bit line in or over a substrate;

forming a conductive layer over the read bit line;

forming a first insulator over the conductive layer;

forming a conductive film;

forming a read word line on a side surface of the conductive layer by anisotropically etching the conductive film.

18. The method of manufacturing a semiconductor memory device according to claim 17,

wherein a word bit line is formed at the step of the forming the read word line.

19. The method of manufacturing a semiconductor memory device according to claim 17, further comprising the step of:

forming a write word line over the conductive layer.

20. The method of manufacturing a semiconductor memory device according to claim 17, further comprising the step of:

forming a semiconductor over the conductive layer, the semiconductor being in contact with the conductive layer.