NON-VOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND METHODS THEREOF

• US 20120213005A1
• Filed: 02/16/2012
• Published: 08/23/2012
• Est. Priority Date: 02/22/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang Hoon
• Application Number:
  US13/398,204
• Publication Number:
  US 20120213005A1
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

The method includes receiving a block address and an erase command output from a controller, and changing, until an erase operation performed according to the erase command on a block corresponding to the block address is completed, a parameter value related to the erase operation. The method further includes storing information corresponding to a finally changed parameter value, and transmitting the information to the controller according to a command output from the controller.

Claims

1. An operation method of a non-volatile memory device comprising:

receiving a block address and an erase command output from a controller;

changing, until an erase operation performed according to the erase command is completed on a block corresponding to the block address, a parameter value related to the erase operation;

storing information corresponding to a finally changed parameter value; and

transmitting the information to the controller according to a command output from the controller.

2. The operation method of claim 1, wherein the command is a read status command requiring information on success or failure of the erase operation.

3. The operation method of claim 2, wherein the parameter value is at least one of time needed until the block is erased, an incremental-step-pulse erase (ISPE) loop count, an incremental-step-pulse erase (ISPE) voltage, at least one of width and amplitude of each erase pulse of each erase loop of the ISPE, at least one of width and amplitude of an erase verify pulse, temperature of the non-volatile memory device, a voltage supplied to the block during the erase operation, and an erase count on the block.

4. The operation method of claim 2, wherein the information is transmitted with a status bit indicating success or failure of the erase operation to the controller.

5. An operation method of a controller comprising:

transmitting, so as to erase a block in a non-volatile memory device, a block address on the block and an erase command to the non-volatile memory device;

transmitting a command to the non-volatile memory device;

receiving information which is output from the non-volatile memory device in response to the command and corresponds to a parameter value related to an erase operation according to the erase command;

analyzing the received information; and

sorting a level of wear-leveling of the block into one of a plurality of groups according to the analyzing.

6. The operation method of claim 5, wherein the command is a read status command requiring information on success or failure of the erase operation.

7. The operation method of claim 6, further comprising:

re-sorting a level of current wear-leveling of the block.

8. The operation method of claim 7, further comprising;

transmitting, by the controller, a result of the sorting or the re-sorting to the non-volatile memory device.

9. The operation method of claim 6, wherein the information indicates at least one of time needed until the block is erased, an incremental-step-pulse erase (ISPE) loop count, an incremental-step-pulse erase (ISPE) voltage, at least one of width and amplitude of each erase pulse of each erase loop of the ISPE, at least one of width and amplitude of an erase verify pulse, temperature of the non-volatile memory device, a voltage supplied to the block during the erase operation, and an erase count on the block.

10. An operational method of a memory system including a non-volatile memory device where a block is embodied and a controller controlling an operation of the non-volatile memory device comprising:

transmitting, by the controller, a block address on the block and an erase command to the non-volatile memory device;

transmitting, by the controller, a command to the non-volatile memory device;

receiving, by the controller, information, which is output from the non-volatile memory device in response to the command and corresponds to a parameter value related to an erase operation according to the erase command;

analyzing, by the controller, the information; and

sorting a level of wear-leveling of the block into one of a plurality of groups according to the analyzing.

11. The operation method of claim 10, further comprising:

changing, by the non-volatile memory device, the parameter value related to the erase operation until the erase operation on the block performed according to the erase command is completed;

storing a finally changed parameter value as the information; and

transmitting, by the non-volatile memory device, the information to the controller, when the command is a read status command, in response to the read status command.

12. The operation method of claim 11, further comprising:

re-sorting, by the controller, a level of wear-leveling of the block, the re-sorting resulting in at least one block changing from one group to another.

13. The operation method of claim 11, wherein the information indicates at least one of time needed until the block is erased, an incremental-step-pulse erase (ISPE) loop count, an incremental-step-pulse erase (ISPE) voltage, at least one of width and amplitude of each erase pulse of each erase loop of the ISPE, at least one of width and amplitude of an erase verify pulse, temperature of the non-volatile memory device, a voltage supplied to the block during the erase operation, and an erase count on the block.

14. The operation method of claim 10, wherein the memory system is a smart card.

15. The operation method of claim 10, wherein the memory system is a solid state drive (SSD).

16-20. -20. (canceled)

21. A method of wear-leveling, comprising:

receiving deterioration information for a block in a non-volatile memory;

determining at least one deterioration indicator based on the deterioration information, the deterioration indicator representing an amount of charge trapped in memory cells of the block; and

sorting the block into a wear-leveling group based on the deterioration indicator.

22. The operation method of claim 21, wherein deterioration information includes at least one of time needed until the block is erased, an incremental-step-pulse erase (ISPE) loop count, an incremental-step-pulse erase (ISPE) voltage, at least one of width and amplitude of each erase pulse of each erase loop of the ISPE, at least one of width and amplitude of an erase verify pulse, temperature of the non-volatile memory device, a voltage supplied to the block during the erase operation, and an erase count on the block.