CONTENT ADDRESSABLE MEMORY

• US 20120215976A1
• Filed: 04/27/2012
• Published: 08/23/2012
• Est. Priority Date: 02/13/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: INOUE, Kazunari
• Granted Patent: US 8,564,998 B2
• Time in Patent Office: Days
• US Class Current: 711/108
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.

Claims

1-8. -8. (canceled)

9. A network equipment comprising:

a central processing unit,

a packet processing unit, which receives data from the Ethernet, and

a content addressable memory,

wherein the central processing unit controls to transfer data from the packet processing unit to the content addressable memory,

wherein the packet processing unit performs analyzing a header of a packet, extracting data, and detecting an address of a next destination, and

wherein the content addressable memory analyzes an address received from the packet processing unit, and comprises;

a memory array including a plurality of memory cells arranged in a matrix and each memory cell row of the memory array storing entry data to be retrieved;

an entry selecting unit for selecting a corresponding entry in the memory array in accordance with a given entry designation signal;

a pre-search unit for generating an entry designation signal for designating a corresponding entry in the memory array in accordance with search data and supplying the entry designation signal to the entry selecting unit;

a plurality of sense amplifiers for detecting and amplifying data stored in an entry selected by the entry selecting unit on a sub-entry unit basis, each sense amplifier being arranged for a respective column of the memory array; and

a comparing/logic processing unit for receiving the search data and output data having a predetermined bit width of the sense amplifiers, comparing the search data and the output data having the predetermined bit width of the sense amplifiers, and generating a signal indicative of a result of the comparison.

10. A network equipment according to claim 9,

wherein the comparing/logic processing circuit includes:

a plurality of match determining circuits for determining a match between output data of the sense amplifiers and the search data, each match determining circuit being arranged for a respective column of said memory array; and

a size comparing circuit for generating a signal indicative of size relation between the output data of the sense amplifiers and the search data.

11. A network equipment according to claim 10,

wherein the size comparing circuit performs the size relation determination in accordance with an output signal of the match determining circuits.

12. A network equipment according to claim 11,

wherein the content addressable memory further comprises a mask decoding circuit for decoding data stored in mask cells in the entry selected by the entry selecting unit and supplying a mask instruction signal indicative of a result of the decoding to a corresponding match determining circuit.