MEMORY PROTECTION IN A DATA PROCESSING SYSTEM

• US 20120215989A1
• Filed: 02/23/2011
• Published: 08/23/2012
• Est. Priority Date: 02/23/2011
• Status: Abandoned Application

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Circello, Joseph C.
• Application Number:
  US13/033,317
• Publication Number:
  US 20120215989A1
• Time in Patent Office: Days
• US Class Current: 711/145
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence

Abstract

A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.

Claims

1. A method comprising:

receiving a first memory access request from a first processor core at a system memory protection unit coupled to a plurality of processor cores including the first processor core, the first memory access request including a first address; and

determining at the system memory protection unit whether the first memory access request is allowed or denied; and

in response to determining the first memory access request is allowed, providing information for storage at a first cache line of a first cache of the first processor core, the information including first access permission information used by the system memory protection unit to determine whether the first memory access request is allowed or denied.

2. The method of claim 1 wherein the first access permission information is associated with the first address and maintained at the system memory protection unit.

3. The method of claim 1 wherein providing the information for storage at the first cache line includes the information including data information or instruction information associated with the first address.

4. The method of claim 1 further comprising:

receiving a second memory access request at the first cache;

determining the second memory access request corresponds to information stored at the first cache line based on an address tag hit at the first cache; and

determining whether to allow or deny the second memory access request based on the first access permission information stored at the first cache line.

5. The method of claim 4 further comprising:

determining at a local memory protection unit of the first processor core that the second memory access request is allowed based upon the access permission information included at the local memory protection unit.

6. The method of claim 1 wherein the first access permission information includes at least one accessibility indicator selected from a group consisting of a supervisor-only access accessibility indicator, a supervisor write accessibility indicator, and a user write accessibility indicator.

7. The method of claim 1 wherein the first access permission information includes at least one accessibility indicator selected from a group consisting of a user write accessibility indicator, and a user read accessibility indicator.

8. The method of claim 1 wherein the first access permission information includes at least one accessibility indicator selected from a group consisting of a supervisor write accessibility indicator, and a supervisor read accessibility indicator.

9. A method comprising:

determining, based upon a first set of information local to a processor core, whether an access request of the processor core is allowed; and

in response to determining the access request resulted in a cache hit at a cache of the processor core, further determining at the processor core based upon a second set of information stored at the cache whether the access request is allowed.

10. The method of claim 9 wherein determining whether the access request is allowed occurs at a first memory protection unit of the processor.

11. The method of claim 9, wherein the second set of information is based upon a third set of information that is not local to the processor core.

12. The method of claim 9, further comprising:

determining whether the access request resulted in the cache hit or in a cache miss; and

subsequent to determining the access request is allowed and to determining the access request resulted in the cache miss, determining, at a location that is not local to the processor core whether further processing of the access request is to be allowed.

13. The method of claim 12, wherein the processor core is a first processor core, and wherein the location that is not local includes a second memory protection unit that is coupled to a plurality of processor cores that includes the first processor core.

14. The method of claim 13, wherein the second memory protection unit determines whether the access request is allowed based upon the third set of information.

15. A system comprising:

a first processor core including a first cache, the first processor core to generate a first memory access request; and

a system memory protection unit to provide first information to be stored in a first cache line of the first cache in response to completion of the first memory access request, the first information including first access permission information determined at the system memory protection unit.

16. The system of claim 15 wherein the first processor core includes a local memory protection unit to allow a second memory access based on the first access permission information stored at the first cache line.

17. The system of claim 16, wherein the local memory protection unit is to further allow the second memory access based on second access permission information stored in the local memory protection unit.

18. The system of claim 15 wherein the system memory protection unit further comprises a storage location to store system access information upon which the first access permission information is based.

19. The system of claim 15 further comprising:

a second processor core including a second cache, the second processor core to generate a second memory access request; and

the system memory protection unit to provide second information to be stored in a second cache line of the second cache in response to completion of the second memory access request, the information including second access permission information determined at the system memory protection unit.

20. The system of claim 19, wherein the system memory protection unit is not to provide the second information to the first processor core for storage at the first cache.