SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD

• US 20120216003A1
• Filed: 02/17/2012
• Published: 08/23/2012
• Est. Priority Date: 02/18/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAKAI, Hiroto, Kanai, Tatsunori, Maeda, Kenichi
• Granted Patent: US 8,892,810 B2
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

Claims

1. A semiconductor device comprising:

a processor; and

a memory device which has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor,

wherein when the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets, and

the processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

2. The device according to claim 1, wherein the tables respectively manage authority, of the worksets, for accessing information in the memory device.

3. The device according to claim 1, wherein the worksets include a first workset and a second workset, and

the tables are updated to allow information for the first workset to be also accessed by the second workset

4. The device according to claim 3, wherein the first workset and the second workset respectively include a first program code and a second program code,

the tables include a first table and a second table, which are respectively associated with the first workset and the second workset, and

when the first workset requires execution of the second program code, the processor transits control from the first workset to the second workset, and switches the table to be used from the first table to the second table.

5. The device according to claim 1, wherein the memory device is managed by a single-address system.

6. The device according to claim 4, further comprising a memory management device configured to access the memory device in response to a request from the processor,

wherein the processor includes:

a creation unit configured to create the first table and the second table;

a first execution unit configured to execute the first program code;

a second execution unit configured to execute the second program code;

a call unit configured to call the second program code from the first workset; and

a control unit configured to transit the control from the first execution unit to the second execution unit in response to a request from the call unit, and

wherein the memory management device accesses the memory device with reference to the first table under the control of the first execution unit, and accesses the memory device with reference to the second table under the control of the second execution unit.

7. The device according to claim 6, wherein the memory device further comprises a volatile semiconductor storage device, and

when data requested from the processor is held in the volatile semiconductor storage device, the memory management device reads out the requested data from the volatile semiconductor storage device, and when the requested data is not held in the volatile semiconductor storage device, the memory management device reads out the requested data from the nonvolatile semiconductor storage device.

8. The device according to claim 1, wherein the processor updates, based on authority for accessing one of the worksets, one of the tables corresponding to the one of the worksets to allow the one of the worksets to access data not included in the one of the worksets.

9. The device according to claim 1, wherein the processor creates new data in response to a request from one of the worksets, and updates one of the tables corresponding to the one of the worksets to set authority for accessing the data.

10. The device according to claim 1, wherein the processor manages pieces of information required to execute the programs as files and directories.

11. A memory protection method of a semiconductor device, which uses a memory device including a nonvolatile semiconductor device as a main memory, the method comprising:

managing, by an operating system, information required to execute a first program as a first workset;

creating, by the operating system, a first table which holds a relationship between information included in the first workset and an address of that information in the memory device;

executing, by the operating system, the first program with reference to the first table;

calling, by the first program, a second program outside the first workset;

managing, by the operating system, information required to execute the second program as a second workset;

creating, by the operating system, a second table which holds a relationship between information included in the second workset and an address of that information in the memory device; and

executing, by the operating system, the second program with reference to the second table.

12. The method according to claim 11, wherein the first table and the second table respectively manage authority, of the first workset and the second workset, for accessing information stored in the memory device.

13. The method according to claim 11, wherein the second table allows information for the first workset to be also accessed by the second workset.

14. The method according to claim 11, wherein the memory device is managed by a single-address system.

15. The method according to claim 11, wherein the memory device further comprises a volatile semiconductor storage device, and

when data requested from a processor is held in the volatile semiconductor storage device, the requested data is read out from the volatile semiconductor storage device, and when the requested data is not held in the volatile semiconductor storage device, the requested data is read out from the nonvolatile semiconductor storage device.

16. The method according to claim 11, further comprising when information not included in the first workset is requested, updating the first table based on authority for accessing of the first workset to allow the first workset to access the information.

17. The method according to claim 11, further comprising

generating, when information, which is not held in the memory device, is requested during execution of the first program, the requested information;

and

updating the first table based on authority for accessing of the first workset to allow the first workset to access the generated information.

18. The method according to claim 11, wherein pieces of information required to execute the first program and the second program are managed as files and directories.