APPARATUS AND METHOD OF SINGLE-INSTRUCTION, MULTIPLE-DATA VECTOR OPERATION MASKING

• US 20120216011A1
• Filed: 02/18/2011
• Published: 08/23/2012
• Est. Priority Date: 02/18/2011
• Status: Abandoned Application

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Gove, Darryl, Weaver, David
• Application Number:
  US13/030,515
• Publication Number:
  US 20120216011A1
• Time in Patent Office: Days
• US Class Current: 712/7
• CPC Class Codes: G06F 15/8053 Vector processors

Abstract

An apparatus, method, and medium for performing a vector operation on portions of one or more source vector registers. A vector unit performs an operation on the source vector registers and only stores results in the target vector register for elements which are selected by the vector operation mask. The vector operation mask can be read by the vector unit or loaded into the vector unit for each instruction cycle. The vector operation mask allows the vector unit to be used with partially filled source vector registers and eliminates the need for scalar operations to be performed on vector data.

Claims

1. An apparatus comprising:

a vector unit, one or more source vectors, and a vector operation mask, wherein each of the one or more source vectors comprises a plurality of N elements, and wherein the vector operation mask comprises a corresponding selection indicator for each of the plurality of N elements;

wherein the vector unit is configured to perform an operation on the one or more source vectors; and

wherein the vector operation mask identifies which of a subset of the plurality of N elements of each of the one or more source vectors are used in the operation to produce a desired result.

2. The apparatus as recited in claim 1, wherein the vector unit performs the operation on a subset of the plurality of N elements of the one or more source vectors, and wherein the indicators in the vector operation mask determine on which of the subset of elements the operation is performed.

3. The apparatus as recited in claim 1, wherein the vector operation mask is either passed to the vector unit as an input during an instruction cycle, or is stored in a register whose location is implied.

4. The apparatus as recited in claim 1, wherein each indicator of the vector operation mask is a single bit, and wherein each element of the plurality of N elements of the one or more source vectors is one or more bits.

5. The apparatus as recited in claim 1, wherein the vector unit comprises a plurality of computing units, and wherein each of the indicators of the vector operation mask are used to enable or disable power to each of the plurality of computing units.

6. The apparatus as recited in claim 1, wherein exceptions corresponding to elements of the plurality of N elements other than said subset are ignored.

7. The apparatus as recited in claim 1, wherein the operation is an arithmetic, logical, load, or store operation.

8. A method for executing a vector operation, the method comprising:

initiating a vector operation;

accessing one or more source vectors, wherein each of the one or more source vectors comprises a plurality of N elements;

accessing a vector operation mask, wherein the vector operation mask comprises a corresponding selection indicator for each of the plurality of N elements of the one or more source vectors;

utilizing the vector operation mask to identify which of a subset of the plurality of N elements of the one or more source vectors are used to produce a desired result; and

generating and conveying a result of the vector operation.

9. The method as recited in claim 8, wherein the vector unit performs the vector operation on a subset of the plurality of N elements of each of the one or more source vectors, and wherein the indicators in the vector operation mask determine on which of the subset of the plurality of N elements the operation is performed.

10. The method as recited in claim 8, wherein the vector operation mask is either passed to the vector unit as an input during an instruction cycle, or is stored in a register whose location is implied.

11. The method as recited in claim 8, wherein each indicator of the vector operation mask is a single bit, and wherein each element of the plurality of N elements of the one or more source vectors is one or more bits.

12. The method as recited in claim 8, wherein the vector unit comprises a plurality of computing units, and wherein each of the indicators of the vector operation mask are used to enable or disable power to each of the plurality of computing units.

13. The method as recited in claim 8, wherein exceptions corresponding to elements of the plurality of N elements other than said subset are ignored.

14. The method as recited in claim 8, wherein the vector operation is an arithmetic, logical, load, or store operation.

15. A computer readable storage medium comprising program instructions to execute a vector operation, wherein when executed the program instructions are operable to:

initiate a vector operation;

access one or more source vectors, wherein each of the one or more source vectors comprises a plurality of N elements;

access a vector operation mask, wherein the vector operation mask comprises a corresponding selection indicator for each of the plurality of N elements of the one or more source vectors;

utilize the vector operation mask to identify which of a subset of the plurality of N elements of the one or more source vectors are used to produce a desired result; and

generate and convey a result of the vector operation.

16. The computer readable storage medium as recited in claim 15, wherein the vector unit performs the vector operation on a subset of the plurality of N elements of each of the one or more source vectors, and wherein the indicators in the vector operation mask determine on which of the subset of the plurality of N elements the operation is performed.

17. The computer readable storage medium as recited in claim 15, wherein the vector operation mask is either passed to the vector unit as an input during an instruction cycle, or is stored in a register whose location is implied.

18. The computer readable storage medium as recited in claim 15, wherein each indicator of the vector operation mask is a single bit, and wherein each element of the plurality of N elements of the one or more source vectors is one or more bits.

19. The computer readable storage medium as recited in claim 15, wherein the vector unit comprises a plurality of computing units, and wherein each of the indicators of the vector operation mask are used to enable or disable power to each of the plurality of computing units.

20. The computer readable storage medium as recited in claim 15, wherein exceptions corresponding to elements of the plurality of N elements other than said subset are ignored.