SEQUENTIAL PROCESSOR COMPRISING AN ALU ARRAY

• US 20120216012A1
• Filed: 10/15/2009
• Published: 08/23/2012
• Est. Priority Date: 10/15/2008
• Status: Active Grant

• Current Assignee: Hyperion Core, Inc.
• Original Assignee: Hyperion Core, Inc.
• Inventors: Vorbach, Martin, May, Frank, Weinhardt, Markus
• Granted Patent: US 9,152,427 B2
• Time in Patent Office: Days
• US Class Current: 712/11
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Claims

1. A single chip sequential processor comprising at least one ALU-Block having

a number of stages of ALUs,

the number being larger than two,

preferably being 4,

a plurality of ALUs within each stage of ALUs,

the plurality preferably consisting

of more than 2 ALUs, in particular of

4 ALUs within one stage

a hardwired interconnection topology for interconnection of said ALUs

the topology preferably allowing for only a one-directional data stream from ALUs in an upstream stage to an ALU in a downstream stage in cases other than feedback from one or more ALUs in one stage to one or more ALUs in the stage immediately upstream or in the stage upstream but the next,

the ALU-Block further having an operand input register file the contents of which are pipelined to stages downstream and

the ALU-Block having register bank arrangements for particular stages,

said sequential processsor capable of maintaining its opcodes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

3. The processing device according to claim 1, wherein

multiple of the datapath units are linked together via multiple of the Register Files;

at least some registers of at least some of the multiple Register Files operating in FIFO mode.

2. A single chip sequential micro-processor, comprising

at least one Instruction Fetcher;

at least one Instruction Decode;

multiple arithmetic-logic units

arranged in an at least two-dimensional pattern within a datapath unit;

a Register File comprising multiple registers;

at least some of the registers selectively operating as either

a single entry read/write register or

a multi entry FIFO unit;

the arithmetic-logic units being connected by a directed one-way bus system;

the directed one-way bus system supporting for each of the arithmetic logic units accessing the results of all arithmetic logic units upstream and the Register File as operand input;

the directed one-way bus system supporting for each of the arithmetic logic units writing result data into at least one of the registers within the Register File.