Controller, A Method Of Operating The Controller And A Memory System

• US 20120216094A1
• Filed: 03/24/2011
• Published: 08/23/2012
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Hyun Jin, Yoo, Sung Joo, Kang, Nam-Wook, Park, Chan Ik
• Granted Patent: US 8,769,378 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

The present disclosure provides a controller which comprises a command generator configured to generate a command to non volatile memory, and buffer configured to receive a first data and a second data and configured to combine the first data and the second data, an ECC unit configured to perform the ECC decoding. And the first page data may include at least one error bit corresponding to an error location table and the second page data may include at least one original bit which can be replaced with the error bit. The buffer may replace the at least one error bit with the said at least one original bit. The error location table may save information of location for the repeated error bit.

Claims

1. A method for operating a controller which controls nonvolatile memory comprising:

applying a read command to non-volatile memory;

receiving first page data and second page data from the non-volatile memory in response to the read command, the second page data including original data and error location information corresponding to the first page data; and

combining the first page data and at least a portion of the original data based on the error location information.

2. The method of claim 1, further comprising:

performing an Error Correction Code (ECC) decoding using the combined data.

3. The method of claim 1, wherein the first page data includes at least one error bit corresponding to a location in the error location information, and

the second page data includes at least one original bit corresponding to the at least one error bit.

4. The method of claim 1, wherein first page data and the second page data are received from different pages.

5. The method of claim 1, wherein the error location information includes a location of a repeated error bit.

6. The method of claim 3, wherein the combining step includes replacing at least one error in the first page data with at least the original bit in the second page data.

7. The method of claim 2, wherein the ECC decoding uses Bose-Ray-Chaudhuri-Hocquenghem (BCH) code.

8. A controller comprising:

a command generator configured to generate a read command for a non volatile memory; and

a buffer configured to receive a first page data and a second page data, the second page data including original data and error location information corresponding to the first page data, the buffer being configured to combine the first page data and at least a portion of the original data based on the error location information.

9. The controller of claim 8, further comprising:

an ECC unit configured to perform Error Correction Code (ECC)decoding on the combined data.

10. The controller of claim 8, wherein the buffer is configured to replace the at least one error bit of the first page data with at least one original bit of the original data.

11. The controller of claim 8, wherein the error location information includes a location of a repeated error bit.

12. A method for operating a controller comprising:

applying a read command to non-volatile memory;

receiving a first page data including at least one error bit, and a second page data corresponding to the first page data from the non-volatile memory in response to the read command, the second page data including error location information and a first Error Correction Code (ECC) data corresponding to the at least one error bit; and

correcting the first page data by performing a first ECC decoding on the at least one error bit using the first ECC data and the error location information.

13. The method of claim 12, further comprising:

performing a second ECC decoding for the corrected first page data.

14. The method of claim 12, wherein the error location table includes a location corresponding to a repeated error bit.

15. The method of claim 12, wherein the first page data and the second page data are received from different pages.

16. The method of claim 12, wherein the first ECC decoding is performed using Reed-Solomon (RS) code and the second ECC decoding is performed using Bose-Ray-Chaudhuri-Hocquenghem (BCH) code.