DESIGN BASED DEVICE RISK ASSESSMENT

• US 20120216169A1
• Filed: 02/17/2012
• Published: 08/23/2012
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Park, Allen, Jin, Youseung, Cho, SungChan, Saville, Barry
• Granted Patent: US 8,656,323 B2
• Time in Patent Office: Days
• US Class Current: 716/136
• CPC Class Codes: G01N 2021/8883 involving the calculation of gauges, generating models
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/32182 If state of tool, product deviates from standard, adjust system, feedback
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01J 37/26 Electron or ion microscopes; Electron or ion diffraction tubes
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The present invention includes defining a multiple patterns of interest utilizing design data of the device; generating a design based classification database, the DBC database including design data associated with each of the POIs; receiving one or more inspection results; comparing the inspection results to each of the plurality of POIs in order to identify an occurrence of at least one of the POIs in the inspection results; determining yield impact of each POI utilizing process yield data; monitoring a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device; and determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device.

Claims

1. A method for design based assessment of a device, comprising:

defining a plurality of patterns of interest utilizing design data of the device;

generating a design based classification database, the design based classification database including design data associated with each of the patterns of interest;

receiving one or more inspection results;

comparing the one or more inspection results to each of the plurality of patterns of interest in order to identify an occurrence of at least one of the patterns of interest in the inspection results;

determining yield impact of each pattern of interest utilizing process yield data;

monitoring a frequency of occurrence of each of the patterns of interest and the criticality of the patterns of interest in order to identify one or more process excursions of the device; and

determining a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons, the critical polygons defined utilizing design data of the device.

2. The method of claim 1, wherein the plurality of patterns of interest are generated utilizing at least one of a failure analysis process, a design rule checking process, an optical rule checking process, or a process window qualification method.

3. The method of claim 1, wherein the process yield data comprises:

end-of-line process yield data.

4. The method of claim 1, wherein the receiving one or more inspection results comprises:

receiving one or more inspection results from a inspection system.

5. The method of claim 4, wherein the inspection system comprises:

at least one of a dark field inspection system or a bright field inspection system.

6. The method of claim 1, wherein the monitoring a frequency of occurrence of each of the patterns of interest and the criticality of the patterns of interest in order to identify one or more process excursions of the device comprises:

generating a Pareto chart configured to determine a ratio of actual defects to expected defects as a function of pattern type.

7. The method of claim 1, wherein the monitoring a frequency of occurrence of each of the patterns of interest and the criticality of the patterns of interest in order to identify one or more process excursions of the device comprises:

performing a statistical process control routine to the plurality of POIs in order to identify one or more process excursions, the one or more process excursions displaying a defect density above a predetermined defect density.

8. The method of claim 1, wherein the critical polygons of the design data are defined utilizing at least one of a design rule checking process, a failure analysis process, or a simulation process.

9. The method of claim 1, further comprising:

providing feedback to a user interface device indicative of a recommended action, wherein the recommended action is a function of the determined risk level for the device.

10. The method of claim 9, wherein the recommended action comprises:

substantially optimizing a design in order to reduce DFM defects.

11. The method of claim 9, wherein the recommended action comprises:

substantially optimizing a process specification.

12. A method for providing dynamic sampling utilizing critical defects, comprising:

identifying a plurality of critical pattern types on a wafer;

determining a device risk level utilizing a calculated risk level and frequency of occurrence for each of the identified critical pattern types;

identifying one or more relevant excursions of the device;

determining dynamic wafer selection in response to the identification of one or more device excursions; and

dynamically sampling at least some of the identified critical pattern types.

13. The method of claim 12, wherein the dynamically sampling at least some of the identified critical pattern types comprises:

sampling some of the critical pattern types based on a frequency of occurrence and a criticality of each of the critical pattern types.

14. The method of claim 12, wherein the dynamically sampling at least some of the identified critical pattern types comprises:

dynamically inspecting at least some of the identified critical pattern types using an inspection tool.

15. A method for providing risk assessment or yield correlation in a memory device, comprising:

defining a plurality of regions based on one or more functional areas of a device utilizing design data;

performing one or more inspection processes on the one or more defined regions;

identifying one or more dies of the one or more defined regions falling below a predetermined control limit utilizing inspection data from the one or more inspection processes; and

identifying regions impacting yield loss by comparing the one or more dies falling below the predetermined control limit to inline data for each of the regions.

16. The method of claim 15, wherein the one or more functional areas of the device comprise:

at least one of a main area of the device, a redundant memory area of the device, or a dummy area of the device.

17. The method of claim 15, wherein the one or more inspection processes comprise:

at least one of dark field inspection or bright field inspection.

18. A method for monitoring device processing using spatial analysis, comprising:

monitoring a process variation signature by inspecting one or more devices between one or more process steps;

associating one or more patterns of interest of the one or more devices with a monitored process variation using a design based classification process; and

identifying one or more equipment signatures using the one or more associated patterns of interest.

19. The method of claim 18, further comprising:

subtracting the identified one or more equipment signatures from a defect map of the device.