PIXEL CIRCUIT AND DISPLAY DEVICE

• US 20120218246A1
• Filed: 10/21/2010
• Published: 08/30/2012
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yamauchi, Yoshimitsu, Ueda, Naoki, Nakano, Fumiki
• Granted Patent: US 8,654,291 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 3/3618 with automatic refresh of the display panel using sense/write circuits
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/367 with a nonlinear element in series with the liquid crystal cell, e.g. a diode, or M.I.M. element

Abstract

A display device in which low power consumption is realized without lowering an aperture ratio is provided. A liquid crystal capacitive element Clc is sandwiched between a pixel electrode 20 and an opposite electrode 80. The pixel electrode 20, one end of a first switch circuit 22, one end of a second switch circuit 23 and a first terminal of a second transistor T2 form an internal node N1. The other terminals of the first switch circuit 22 and the second switch circuit 23 are connected to a source line SL. The second switch circuit 23 is a series circuit composed of a first transistor T1 and a diode D1. A control terminal of the first transistor T1, a second terminal of the second transistor T2 and one end of a boost capacitive element Cbst form an output node N2. The other end of the boost capacitive element Cbst and the control terminal of the second transistor T2 are connected to a boost line BST and a reference line REF, respectively. The diode D1 has a rectifying function from the source line SL to the internal node N1.

Claims

1. A pixel circuit comprising:

a display element part including a unit display element;

an internal node composing a part of the display element part, for holding a pixel data voltage applied to the display element part;

a first switch circuit for transferring the pixel data voltage supplied from a data signal line to the internal node through at least a predetermined switch element;

a second switch circuit for transferring a voltage supplied from the data signal line to the internal node without passing through the predetermined switch element; and

a control circuit for holding a predetermined voltage depending on the pixel data voltage held by the internal node at one end of a first capacitive element, and controlling ON/OFF of the second switch circuit, wherein

the second switch circuit is a series circuit comprising a first transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, and a diode element,

the control circuit is a series circuit comprising a second transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, and the first capacitive element,

one end of each of the first and second switch circuits is connected to the data signal line,

the other end of each of the first and second switch circuits, and the first terminal of the second transistor element are connected to the internal node,

the diode element has a rectifying function from the data signal line to the internal node,

the control terminal of the first transistor element, the second terminal of the second transistor element, and one end of the first capacitive element are connected to each other to form an output node of the control circuit,

the control terminal of the second transistor element is connected to a first control line, and

the other end of the first capacitive element is connected to a second control line.

2. The pixel circuit according to claim 1, wherein

the predetermined switch element comprises a third transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, and

the control terminal of the third transistor element is connected to a scan signal line.

3. The pixel circuit according to claim 1, wherein

the second switch circuit is a series circuit comprising the first transistor element, the diode element, and a fourth transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, and

the control terminal of the fourth transistor element is connected to the second control line or a third control line.

4. The pixel circuit according to claim 3, wherein

the first switch circuit is a series circuit comprising the fourth transistor element in the second switch circuit and the predetermined switch element, or a series circuit comprising a fifth transistor element having a control terminal connected to the control terminal of the fourth transistor element in the second switch circuit and the predetermined switch element.

5. The pixel circuit according to claim 1, further comprising:

a second capacitive element having one end connected to the internal node, and the other end connected to a fourth control line or a predetermined fixed voltage line.

6. A display device in which

a pixel circuit array comprises a plurality of pixel circuits, each according to claim 1, arranged in a row direction and a column direction,

the data signal line is provided with respect to each of the columns,

one end of the first switch circuit in each of the pixel circuits arranged in the same column is connected to a common data signal line,

the control terminal of the second transistor element in each of the pixel circuits arranged in the same row or the same column is connected to a common first control line, and

the other end of the first capacitive element in each of the pixel circuits arranged in the same row or the same column is connected to a common second control line, the display device comprising:

a data signal line drive circuit for driving the data signal lines individually; and

a control line drive circuit for driving the first and second control lines individually.

7. The display device according to claim 6, wherein

the predetermined switch element is a third transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, the control terminal being connected to a scan signal line,

the scan signal line is provided with respect to each of the rows, and the pixel circuits arranged in the same row are connected to a common scan signal line, and

a scan signal line drive circuit for driving the scan signal lines individually is provided.

8. The display device according to claim 7, wherein

the second switch circuit is a series circuit comprising the first transistor element, the diode element, and a fourth transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals, and

the control terminal of the fourth transistor element in each of the pixel circuits arranged in the same row or the same column is connected to the common second control line.

9. The display device according to claim 7, wherein

the second switch circuit is a series circuit comprising the first transistor element, the diode element, and a fourth transistor element having a first terminal, a second terminal, and a control terminal for controlling connection between the first and second terminals,

the control terminal of the fourth transistor element in each of the pixel circuits arranged in the same row or the same column is connected to a common third control line, and

the control line drive circuit drives the first to third control lines, individually.

10. The display device according to claim 8, wherein

the first switch circuit is a series circuit comprising the fourth transistor element in the second switch circuit, and the third transistor element, or a series circuit comprising a fifth transistor element having a control terminal connected to the control terminal of the fourth transistor element in the second switch circuit, and the third transistor element.

11. The display device according to claim 9, wherein

the first switch circuit is a series circuit comprising the fourth transistor element in the second switch circuit, and the third transistor element, or a series circuit comprising a fifth transistor element having a control terminal connected to the control terminal of the fourth transistor element in the second switch circuit, and the third transistor element.

12. The display device according to claim 7, wherein

at a time of a writing action for writing the pixel data in the pixel circuits arranged in one selected row individually,

the scan signal line drive circuit applies a predetermined selected row voltage to the scan signal line in the selected row to turn on the third transistor elements arranged in the selected row, and applies a predetermined unselected row voltage to the scan signal line in an unselected row to turn off the third transistor elements arranged in the unselected row, and

the data signal line drive circuit applies a data voltage corresponding to the pixel data to be written in the pixel circuit in each column in the selected row, to the data signal lines, individually.

13. The display device according to claim 12, wherein

at the time of the writing action,

the control line drive circuit applies a predetermined voltage to the first control line to turn on the second transistor element.

14. The display device according to claim 10, wherein

at a time of a writing action for writing the pixel data in the pixel circuits arranged in one selected row individually,

the scan signal line drive circuit applies a predetermined selected row voltage to the scan signal line in the selected row to turn on the third transistor elements arranged in the selected row, and applies a predetermined unselected row voltage to the scan signal line in an unselected row to turn off the third transistor elements arranged in the unselected row,

the control line drive circuit applies a predetermined selecting voltage to the second control line arranged in the selected row to turn on the fourth transistor elements, and applies a predetermined non-selecting voltage to the second control line in the unselected row to turn off the fourth transistor elements, and

the data signal line drive circuit applies a data voltage corresponding to the pixel data to be written in the pixel circuit in each column in the selected row, to the data signal lines, individually.

15. The display device according to claim 11, wherein

at a time of a writing action for writing the pixel data in the pixel circuits arranged in one selected row individually,

the scan signal line drive circuit applies a predetermined selected row voltage to the scan signal line in the selected row to turn on the third transistor elements arranged in the selected row, and applies a predetermined unselected row voltage to the scan signal line in an unselected row to turn off the third transistor elements arranged in the unselected row,

the control line drive circuit applies a predetermined selecting voltage to the third control line arranged in the selected row to turn on the fourth transistor elements, and applies a predetermined non-selecting voltage to the third control line in the unselected row to turn off the fourth transistor elements, and

the data signal line drive circuit applies a data voltage corresponding to the pixel data to be written in the pixel circuit in each column in the selected row, to the data signal lines, individually.

16. The display device according to claim 7, wherein

the internal node of each of the pixel circuits in the pixel circuit array holds one voltage state among a plurality of discrete voltage states, in which multi-gradation is implemented by the different voltage states, and

at a time of a self refreshing action for compensating voltage fluctuations of the internal nodes at the same time by activating the second switch circuits and the control circuits in the plurality of pixel circuits,

the scan signal line drive circuit applies a predetermined voltage to the scan signal lines connected to all the pixel circuits in the pixel circuit array to turn off the third transistor elements,

the data signal line drive circuit applies a refreshing input voltage provided by adding a predetermined first adjusting voltage corresponding to a voltage drop in the second switch circuit, to a refreshing desired voltage corresponding to the voltage state of a target gradation to be subjected to a refreshing action, to the data signal line, and

the control line drive circuit applies a refreshing reference voltage provided by adding a predetermined second adjusting voltage corresponding to a voltage drop in the first control line and the internal node, to a refreshing isolation voltage defined by a middle voltage between a voltage state of a gradation one step lower than the target gradation and the voltage state of the target gradation, to the first control line, and applies a boost voltage having a predetermined amplitude to the second control line to apply a voltage change due to capacitive coupling through the first capacitive element, to the output node, and

when the voltage state of the internal node is higher than the refreshing desired voltage, the diode element is reversely biased from the data signal line to the internal node, and the data signal line and the internal node are not connected, when the voltage state of the internal node is lower than the refreshing isolation voltage, a potential fluctuation of the output node due to the boost voltage application is suppressed, the first transistor element is turned off, and the data signal line and the internal node are not connected, and when the voltage state of the internal node is higher than the refreshing isolation voltage and lower than the refreshing desired voltage, the diode element is forwardly biased from the data signal line to the internal node, the potential fluctuation of the output node is not suppressed, the first transistor element is turned on, and the refreshing desired voltage is applied to the internal node, so that the refreshing action is executed for the pixel circuit having the internal node showing the voltage state of the target gradation.

17. The display device according to claim 8, wherein

the internal node of each of the pixel circuits in the pixel circuit array holds one voltage state among a plurality of discrete voltage states, in which multi-gradation is implemented by the different voltage states, and

at a time of a self refreshing action for compensating voltage fluctuations of the internal nodes at the same time by activating the second switch circuits and the control circuits in the plurality of pixel circuits,

the scan signal line drive circuit applies a predetermined voltage to the scan signal lines connected to all the pixel circuits in the pixel circuit array to turn off the third transistor elements,

the data signal line drive circuit applies a refreshing input voltage provided by adding a predetermined first adjusting voltage corresponding to a voltage drop in the second switch circuit, to a refreshing desired voltage corresponding to the voltage state of a target gradation to be subjected to a refreshing action, to the data signal line, and

the control line drive circuit applies a refreshing reference voltage provided by adding a predetermined second adjusting voltage corresponding to a voltage drop in the first control line and the internal node, to a refreshing isolation voltage defined by a middle voltage between a voltage state of a gradation one step lower than the target gradation and the voltage state of the target gradation, to the first control line, and applies a boost voltage having a predetermined amplitude to the second control line to apply a voltage change due to capacitive coupling through the first capacitive element, to the output node, and

when the voltage state of the internal node is higher than the refreshing desired voltage, the diode element is reversely biased from the data signal line to the internal node, and the data signal line and the internal node are not connected, when the voltage state of the internal node is lower than the refreshing isolation voltage, a potential fluctuation of the output node due to the boost voltage application is suppressed, the first transistor element is turned off, and the data signal line and the internal node are not connected, and when the voltage state of the internal node is higher than the refreshing isolation voltage and lower than the refreshing desired voltage, the diode element is forwardly biased from the data signal line to the internal node, the potential fluctuation of the output node is not suppressed, the first transistor element is turned on, and the refreshing desired voltage is applied to the internal node, so that the refreshing action is executed for the pixel circuit having the internal node showing the voltage state of the target gradation.

18. The display device according to claim 9, wherein

the internal node of each of the pixel circuits in the pixel circuit array holds one voltage state among a plurality of discrete voltage states, in which multi-gradation is implemented by the different voltage states, and

at a time of a self refreshing action for compensating voltage fluctuations of the internal nodes at the same time by activating the second switch circuits and the control circuits in the plurality of pixel circuits,

the scan signal line drive circuit applies a predetermined voltage to the scan signal lines connected to all the pixel circuits in the pixel circuit array to turn off the third transistor elements,

the data signal line drive circuit applies a refreshing input voltage provided by adding a predetermined first adjusting voltage corresponding to a voltage drop in the second switch circuit, to a refreshing desired voltage corresponding to the voltage state of a target gradation to be subjected to a refreshing action, to the data signal line, and

the control line drive circuit applies a refreshing reference voltage provided by adding a predetermined second adjusting voltage corresponding to a voltage drop in the first control line and the internal node, to a refreshing isolation voltage defined by a middle voltage between a voltage state of a gradation one step lower than the target gradation and the voltage state of the target gradation, to the first control line, applies a predetermined voltage to the third control line to turn on the fourth transistor element, and applies a boost voltage having a predetermined amplitude to the second control line to apply a voltage change due to capacitive coupling through the first capacitive element, to the output node, and

when the voltage state of the internal node is higher than the refreshing desired voltage, the diode element is reversely biased from the data signal line to the internal node, and the data signal line and the internal node are not connected, when the voltage state of the internal node is lower than the refreshing isolation voltage, a potential fluctuation of the output node due to the boost voltage application is suppressed, the first transistor element is turned off, and the data signal line and the internal node are not connected, and when the voltage state of the internal node is higher than the refreshing isolation voltage and lower than the refreshing desired voltage, the diode element is forwardly biased from the data signal line to the internal node, the potential fluctuation of the output node is not suppressed, the first transistor element is turned on, and the refreshing desired voltage is applied to the internal node, so that the refreshing action is executed for the pixel circuit having the internal node showing the voltage state of the target gradation.

19. The display device according to claim 16, wherein

under the condition that the third transistor element is turned off, the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the action to apply the boost voltage to the second control line is executed several times while changing the values of the refreshing input voltage and the refreshing isolation voltage, so that the refreshing action is sequentially executed for the pixel circuits having the internal nodes showing the voltage states of different gradations.

20. The display device according to claim 19, wherein

the boost voltage is applied while the refreshing input voltage and the refreshing isolation voltage are changed the number of times provided by subtracting one from the number of gradations corresponding to the number of the voltage states held by the internal node of each of the pixel circuits in the pixel circuit array.

21. The display device according to claim 19, wherein

after completion of a refreshing step including an action in which the action to apply the boost voltage to the second control line is executed several times while changing the values of the refreshing input voltage and the refreshing isolation voltage under the condition that the third transistor element is turned off, the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line,

a stand-by step is executed in such a manner that the data signal line drive circuit applies a voltage corresponding to a minimum value of the voltage state held by the internal node to the data signal line, and the control line drive circuit does not apply the boost voltage to the second control line, and applies a voltage to the first control line over at least a given time to turn on the second transistor element regardless of the voltage state of the internal node.

22. The display device according to claim 21, wherein

after the stand-by step is executed over a time which is ten times as long as that of the refreshing step, the refreshing step is executed again.

23. The display device according to claim 16, wherein

the first adjusting voltage is a turn-on voltage of the diode element.

24. The display device according to claim 16, wherein

the second adjusting voltage is a threshold voltage of the second transistor element.

25. The display device according to claim 9, wherein

the internal node of each of the pixel circuits in the pixel circuit array holds one voltage state among a plurality of discrete voltage states, in which multi-gradation is implemented by the different voltage states, and

at a time of a self refreshing action for compensating voltage fluctuations of the internal nodes at the same time by activating the second switch circuits and the control circuits in the plurality of pixel circuits,

the scan signal line drive circuit applies a predetermined voltage to the scan signal lines connected to all the pixel circuits in the pixel circuit array to turn off the third transistor elements,

the data signal line drive circuit applies a refreshing input voltage provided by adding a predetermined first adjusting voltage corresponding to a voltage drop in the second switch circuit, to a refreshing desired voltage corresponding to the voltage state of a target gradation to be subjected to a refreshing action, to the data signal line, and

the control line drive circuit applies a refreshing reference voltage provided by adding a predetermined second adjusting voltage corresponding to a voltage drop in the first control line and the internal node, to a refreshing isolation voltage defined by a middle voltage between a voltage state of a gradation one step lower than the target gradation and the voltage state of the target gradation, to the first control line, applies a boost voltage having a predetermined amplitude to the second control line to apply a voltage change due to capacitive coupling through the first capacitive element, to the output node, and applies a predetermined voltage to the third control line to turn on the fourth transistor element, and

when the voltage state of the internal node is higher than the refreshing desired voltage, the diode element is reversely biased from the data signal line to the internal node, and the data signal line and the internal node are not connected, when the voltage state of the internal node is lower than the refreshing isolation voltage, a potential fluctuation of the output node due to the boost voltage application is suppressed, the first transistor element is turned off, and the data signal line and the internal node are not connected, and when the voltage state of the internal node is higher than the refreshing isolation voltage and lower than the refreshing desired voltage, the diode element is forwardly biased from the data signal line to the internal node, the potential fluctuation of the output node is not suppressed, the first transistor element is turned on, and the refreshing desired voltage is applied to the internal node, so that the refreshing action is executed for the pixel circuit having the internal node showing the voltage state of the target gradation.

26. The display device according to claim 16, wherein

at the time of the self refreshing action,

under a condition that a first gradation is set as the target gradation, the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the boost voltage is applied to the second control line, and then

with the boost voltage continuously applied, a second gradation one step higher than the first gradation is set as the target gradation, the refreshing reference voltage applied to the first control line is changed, and thereafter the refreshing input voltage applied to the data signal line is changed, so that the refreshing action is sequentially executed for the pixel circuits having the internal nodes showing the voltage states of different gradations.

27. The display device according to claim 26, wherein

in a case where a gradation higher than the second gradation exists,

after completion of the refreshing action for the second gradation, with the boost voltage continuously applied, an action is repeatedly executed in such a manner that a one step higher gradation is set as the target gradation, the refreshing reference voltage applied to the first control line is changed, and thereafter the refreshing input voltage applied to the data signal line is changed.

28. The display device according to claim 18, wherein

at the time of the self refreshing action,

under a condition that a first gradation is set as the target gradation, the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the boost voltage is applied to the second control line, and a predetermined voltage is applied to the third control line to turn on the fourth transistor element, and then

with the boost voltage and the predetermined voltage to turn on the fourth transistor element continuously applied, a second gradation one step higher than the first gradation is set as the target gradation, the refreshing reference voltage applied to the first control line is changed, and thereafter the refreshing input voltage applied to the data signal line is changed, so that the refreshing action is sequentially executed for the pixel circuits having the internal nodes showing the voltage states of different gradations.

29. The display device according to claim 25, wherein

at the time of the self refreshing action,

under a condition that a first gradation is set as the target gradation, the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the boost voltage is applied to the second control line, and a predetermined voltage is applied to the third control line to turn on the fourth transistor element, and then

with the boost voltage and the predetermined voltage to turn on the fourth transistor element continuously applied, a second gradation one step higher than the first gradation is set as the target gradation, the refreshing reference voltage applied to the first control line is changed, and thereafter the refreshing input voltage applied to the data signal line is changed, so that the refreshing action is sequentially executed for the pixel circuits having the internal nodes showing voltage states of different gradations.

30. The display device according to claim 28, wherein

in a case where a gradation higher than the second gradation exists,

after completion of the refreshing action for the second gradation, with the boost voltage and the predetermined voltage to turn on the fourth transistor element continuously applied, an action is repeatedly executed in such a manner that a one step higher gradation is set as the target gradation, the refreshing reference voltage applied to the first control line is changed, and thereafter the refreshing input voltage applied to the data signal line is changed.

31. The display device according to claim 16, wherein

the second control lines connected to the other ends of the first capacitive elements of the pixel circuits arranged in odd-numbered rows or odd-numbered columns are electrically connected to each other,

the second control lines connected to the other ends of the first capacitive elements of the pixel circuits arranged in even-numbered rows or even-numbered columns are electrically connected to each other, and

the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the odd-numbered row or the odd-numbered column and the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the even-numbered row or the even-numbered column are not electrically connected to each other, and driven by the control line drive circuit individually.

32. The display device according to claim 17, wherein

the second control lines connected to the other ends of the first capacitive elements of the pixel circuits arranged in odd-numbered rows or odd-numbered columns are electrically connected to each other,

the second control lines connected to the other ends of the first capacitive elements of the pixel circuits arranged in even-numbered rows or even-numbered columns are electrically connected to each other, and

the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the odd-numbered row or the odd-numbered column and the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the even-numbered row or the even-numbered column are not electrically connected to each other, and driven by the control line drive circuit individually.

33. The display device according to claim 18, wherein

the second control lines connected to the other ends of the first capacitive elements, and the third control lines connected to the control terminals of the forth transistor elements are electrically connected to each other, respectively in the pixel circuits arranged in odd-numbered rows or odd-numbered columns,

the second control lines connected to the other ends of the first capacitive elements, and the third control lines connected to the control terminals of the forth transistor elements are electrically connected to each other, respectively in the pixel circuits arranged in even-numbered rows or even-numbered columns,

the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the odd-numbered row or the odd-numbered column, and the second control line connected to the other end of the first capacitive element of each of the pixel circuits arranged in the even-numbered row or the even-numbered column are not electrically connected to each other, and driven by the control line drive circuit individually, and

the third control line connected to the control terminal of the fourth transistor terminal of each of the pixel circuits arranged in the odd-numbered row or the odd-numbered column, and the third control line connected to the control terminal of the fourth transistor terminal of each of the pixel circuits arranged in the even-numbered row or the even-numbered column are not electrically connected to each other, and driven by the control line drive circuit individually.

34. The display device according to claim 31, wherein

a terminal, which is opposite to a terminal connected to the internal node, of the terminals of the unit display element is connected to a common electrode, and

the writing is performed in such a manner that at the time of the writing action for writing the pixel data in the pixel circuit, a polarity of a potential of the internal node based on a potential of the common electrode is changed between the pixel circuits arranged in the odd-numbered row or the odd-numbered column, and the pixel circuits arranged in the even-numbered row or the even-numbered column.

35. The display device according to claim 34, wherein

two high and low voltages are allowed to be applied to the common electrode, and

the two high and low voltages to be applied to the common electrode are switched between a period to perform the writing action for the pixel circuits arranged in the odd-numbered row or the odd-numbered column, and a period to perform the writing action for the pixel circuits arranged in the even-numbered row or the even-numbered column.

36. The display device according to claim 35, wherein

the refreshing action is executed for the pixel circuits arranged in the odd-numbered row or the odd-numbered column in such a manner that under a condition that one of the high and low voltages is applied to the common electrode, the third transistor element is turned off, and under a condition that the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the boost voltage is applied to the second control line connected to the odd-numbered row or the odd-numbered column, and

the refreshing action is executed for the pixel circuits arranged in the even-numbered row or the even-numbered column in such a manner that after the voltage applied to the common electrode is switched to the other of the high and low voltages, under the condition that the refreshing input voltage is applied to the data signal line, and the refreshing reference voltage is applied to the first control line, the boost voltage is applied to the second control line connected to the even-numbered row or the even-numbered column.