SYSTEM, METHOD, AND DEVICE TO DISTRIBUTE ACCURATE SYNCHRONIZATION TIMESTAMPS IN AN EXPANDABLE AND TIMING CRITICAL SYSTEM

• US 20120219099A1
• Filed: 02/25/2011
• Published: 08/30/2012
• Est. Priority Date: 02/25/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Loukianov, Dmitrii
• Granted Patent: US 8,971,470 B2
• Time in Patent Office: Days
• US Class Current: 375/357
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node

Abstract

Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.

Claims

1. A device comprising:

an interface to an interconnect system;

a time base comprising a clock and a time counter which increments or decrements its count each period of the clock;

a time stamp generator to capture a count of the time base associated with the device, the time stamp generator to use the interface to transmit a time stamp event indicator to the interconnect system and also to transmit a device identifier to the interconnect system, wherein the interface is to transmit signals to simultaneously initiate a time stamping event in one or more other devices and to trigger transmission by the one or more other devices of device identifiers and timestamps to the interconnect system; and

collision avoidance logic to determine whether the device is permitted to transmit its time stamp using the interconnect system, wherein the time stamp generator is to wait for a period of time and transmit the device identifier to the interconnect system again in response to the device not being permitted to transmits its time stamp.

2. The device of claim 1, wherein the interface is configured in one of:

an open collector, open drain, and a wired-OR configuration.

3. The device of claim 1, wherein the interface comprises a bidirectional optical interconnect system and communication of bits occurs by modulating optical radiation and wherein collision avoidance logic is to detect collisions by monitoring optical signal intensity or phase to determine if a signal different from that transmitted by the interface is communicated by the interconnect system.

4. The device of claim 1, wherein the time stamp event indicator is to trigger at least one other device communicatively coupled to the interconnect system to determine its time stamp, to transmit its device identifier to the interconnect system, and to transmit its coordinated time stamp to the interconnect system if its device identifier is the lowest value.

5. The device of claim 1, wherein the collision avoidance logic is to determine that the time stamp generator is permitted to transmit its time stamp using the interface if the associated device identifier is the lowest value.

6. The device of claim 1, wherein the collision avoidance logic is utilize a collision-avoidance protocol compliant with I2C.

7. The device of claim 1, further comprising:

in response to the again transmitted device identifier being the lowest value, the time stamp generator is to transmit the time stamp associated with the device identifier to the interconnect system using the interface.

8. The device of claim 1, further comprising:

time stamp storage to store any time stamp received from the interconnect system.

9. The device of claim 1, wherein the interconnect system comprises a single or two wire hardware interconnect.

10. The device of claim 1, further comprising:

a clock adjuster logic to compare received time stamps with the time stamp of the device to measure drift errors and to adjust an oscillator frequency of a clock used by the device to synchronize with one of the received time stamps.

11. A method comprising:

each of at least two devices coupled to an interconnect receiving an indication to determine its time stamp;

each of the at least two devices determining its time stamp;

each of the at least two devices transmitting its identifier to the interconnect;

a device with the lowest identifier transmitting its time stamp to the interconnect;

each of the at least two devices, other than the device with the lowest identifier, receiving the time stamp;

each of the at least two devices, other than the device with the lowest identifier, transmitting its identifier to the interconnect; and

a second device with the second lowest identifier transmitting its time stamp to the interconnect.

12. The method of claim 11, wherein each of the at least two devices that receives a time stamp from another device synchronizes its clock to a clock of one of the devices.

13. The method of claim 11, wherein each of the at least two devices that receives a time stamp from another device synchronizes its clock to a network or multi-media clock of one of the devices.

14. The method of claim 11, wherein each of the at least two devices is an independent module or integrated circuit.

15. The method of claim 11, wherein each of the at least two devices are selected from among a wireless or wired network interface, an audio encoder, an audio decoder, a video encoder, and a video decoder.

16. A system comprising:

a network medium;

a network interface communicatively coupled to the network medium;

an interconnect;

a plurality of devices communicatively coupled to the interconnect, wherein each of the devices comprises;

an interface to the interconnect;

a time base comprising a clock and a time counter which increments or decrements its count each period of the clock;

a time stamp generator to capture a count of the time base associated with the device, the time stamp generator to use the interface to transmit a time stamp event indicator to the interconnect and also to transmit a device identifier to the interconnect, wherein the interface is to transmit signals to simultaneously initiate a time stamping event in one or more other devices and to trigger transmission by the one or more other devices of device identifiers and timestamps to the interconnect; and

collision avoidance logic to determine whether the device is permitted to transmit its time stamp using the interconnect, wherein the time stamp generator is to wait for a period of time and transmit the device identifier to the interconnect again in response to the device not being permitted to transmits its time stamp.

17. The system of claim 16, wherein the interface is configured in one of:

an open collector, open drain, and a wired-OR configuration.

18. The system of claim 16, wherein the time stamp event indicator is to trigger at least one other device communicatively coupled to the interconnect to determine its time stamp, to transmit its device identifier to the interconnect, and to transmit its coordinated time stamp to the interconnect if its device identifier is the lowest value.

19. The system of claim 16, wherein the interconnect comprises a single or two wire hardware interconnect.

20. The system of claim 16, wherein each of the devices further comprises:

a clock adjuster logic to compare received time stamps with the time stamp of the device to measure drift errors and to adjust an oscillator frequency of a clock used by the device to synchronize with one of the received time stamps.