METHOD OF FORMING A HYBRID SPLIT GATE SIMICONDUCTOR

• US 20120220092A1
• Filed: 04/30/2012
• Published: 08/30/2012
• Est. Priority Date: 10/21/2009
• Status: Abandoned Application

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Bobde, Madhur, Chen, Qufei, Azam, Misbah Ul, Terrill, Kyle, Gao, Yang, Shi, Sharon
• Application Number:
  US13/460,600
• Publication Number:
  US 20120220092A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches.

Claims

1. A method comprising:

forming a plurality of first trenches in a semiconductor substrate to a first depth;

forming a plurality of second trenches in said semiconductor substrate to a second depth;

wherein said plurality of first trenches are parallel with said plurality of second trenches, and

wherein further trenches of said plurality of first trenches alternate with and are adjacent to trenches of said plurality of second trenches.

2. The method of claim 1 further comprising:

filling said plurality of first trenches with a first polysilicon.

3. The method of claim 2 further comprising:

masking said plurality of first trenches prior to said filling.

4. The method of claim 2 further comprising:

filling said plurality of first trenches with a second polysilicon, above said first polysilicon.

5. The method of claim 4 further comprising:

forming an oxide in said plurality of first trenches, said oxide separating said first and second polysilicon.

6. The method of claim 3 further comprising:

filling said plurality of second trenches with said second polysilicon, at substantially the same depth as said second polysilicon in said plurality of first trenches.

7. The method of claim 1 further comprising:

doping regions between said first plurality and second plurality of trenches to form a body region.

14. The method of claim 1 further comprising:

doping regions between said trenches to form a plurality of source regions.

8. A method comprising:

forming a plurality of trenches in a semiconductor substrate to a first depth,

wherein trenches of said plurality of trenches are parallel to one another;

masking alternate trenches of said plurality of trenches; and

increasing the depth of unmasked trenches of said plurality of trenches to a second depth.

9. The method of claim 8 wherein a patterned layer of pad oxide forms a mask for said increasing.

10. The method of claim 8 further comprising:

filling unmasked trenches of said plurality of trenches with a first polysilicon.

11. The method of claim 8 further comprising:

forming an oxide in said unmasked trenches above said first polysilicon.

12. The method of claim 11 further comprising:

filling said plurality of trenches with second polysilicon.

13. The method of claim 8 further comprising:

forming a pad oxide on said semiconductor substrate.

15. A method comprising:

forming a vertical trench metal oxide semiconductor field effect transistor (MOSFET) device comprising a plurality of parallel filled-trench structures,

wherein said parallel filled-trench structures are spaced at a pitch distance of 0.6 microns or less, and

wherein each of said parallel filled-trench structures comprise a gate structure of said MOSFET.

16. The method of claim 15 wherein said forming comprises:

first forming a first plurality of first trenches in a semiconductor substrate to a first depth;

second forming a second plurality of second trenches in said semiconductor substrate to a second depth; and

wherein said first trenches alternate with said second trenches.

17. The method of claim 16 wherein said second forming comprises:

masking said first trenches; and

increasing a depth of said second trenches to said second depth.

18. The method of claim 16 wherein said forming further comprises:

filling said first trenches with a first polysilicon.

19. The method of claim 18 wherein said forming further comprises:

filling said first and second trenches with a second polysilicon.

20. The method of claim 15 wherein said forming comprises:

doping regions between said parallel filled-trench structures to form a body region.