SYSTEM AND METHOD FOR EMPLOYING SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION CONCURRENTLY IN MULTIPLE SCENARIOS TO REDUCE DYNAMIC POWER IN AN ELECTRONIC CIRCUIT AND AN APPARATUS INCORPORATING THE SAME
First Claim
1. A dynamic power recovery system, comprising:
- a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, said initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of said at least one path based on said first conditional downsizings; and
a speed recovery module associated with said power recovery module and configured to carry out a speed recovery process in each of said multiple scenarios concurrently, said speed recovery process including determining whether said first conditional downsizings cause a timing violation with respect to said at least one path and making second conditional upsizings with higher dynamic power cells until said timing violation is removed.
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Abstract
A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.
13 Citations
22 Claims
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1. A dynamic power recovery system, comprising:
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a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, said initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of said at least one path based on said first conditional downsizings; and a speed recovery module associated with said power recovery module and configured to carry out a speed recovery process in each of said multiple scenarios concurrently, said speed recovery process including determining whether said first conditional downsizings cause a timing violation with respect to said at least one path and making second conditional upsizings with higher dynamic power cells until said timing violation is removed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A dynamic power recovery method carried out in each of multiple scenarios concurrently, comprising:
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making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells; estimating a delay and a slack of said at least one path based on said first conditional downsizing; determining whether said first conditional downsizings cause a timing violation with respect to said at least one path; making second conditional upsizings with higher dynamic power cells until said timing violation is removed; and merging and applying said downsizings and upsizings and updating timing with respect to said each of said multiple scenarios. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. An electronic design automation tool, comprising:
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an initial power recovery module configured to identify cells in positive timing margin paths of a circuit design and provide downsized cells for said cells that have a lower dynamic power thereof, said cells complying with a timing signoff of said circuit design; and a speed recovery module configured to determine timing violations caused by employing said downsized cells for said cells and upsize back a minimum amount of said downsized cells to correct said timing violations.
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22. An apparatus, comprising:
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circuitry for making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells; circuitry for estimating a delay and a slack of said at least one path based on said first conditional downsizing; circuitry for determining whether said first conditional downsizings cause a timing violation with respect to said at least one path; circuitry for making second conditional upsizings with higher dynamic power cells until said timing violation is removed; and circuitry for merging and applying said downsizings and upsizings and updating timing with respect to said each of said multiple scenarios.
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Specification