DENSE ARRAYS AND CHARGE STORAGE DEVICES
First Claim
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1. A memory device, comprising:
- a substrate;
a first contact located over the substrate;
a vertical semiconductor pillar located over the first contact, a first end of the vertical semiconductor pillar contacting the first contact;
a second contact located over the vertical semiconductor pillar, wherein a second end of the vertical semiconductor pillar contacts the second contact;
a charge storage region located adjacent to a first side of the vertical semiconductor pillar;
a control gate located adjacent to the charge storage region;
a tunneling dielectric layer located between the first side of the vertical semiconductor pillar and charge storage region, and between the first contact and the control gate; and
a blocking dielectric layer located between the charge storage region and the control gate, and between the first contact and the control gate;
wherein the control gate is located entirely above the first contact.
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Abstract
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
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Citations
20 Claims
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1. A memory device, comprising:
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a substrate; a first contact located over the substrate; a vertical semiconductor pillar located over the first contact, a first end of the vertical semiconductor pillar contacting the first contact; a second contact located over the vertical semiconductor pillar, wherein a second end of the vertical semiconductor pillar contacts the second contact; a charge storage region located adjacent to a first side of the vertical semiconductor pillar; a control gate located adjacent to the charge storage region; a tunneling dielectric layer located between the first side of the vertical semiconductor pillar and charge storage region, and between the first contact and the control gate; and a blocking dielectric layer located between the charge storage region and the control gate, and between the first contact and the control gate; wherein the control gate is located entirely above the first contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of making a memory device, comprising:
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forming a first contact layer over a substrate; forming a first semiconductor layer having a first conductivity type over the first contact layer; forming a second semiconductor layer having a second conductivity type over the first semiconductor layer; forming a third semiconductor layer having the first conductivity type over the second semiconductor layer; patterning the first, second and third semiconductor layers to form semiconductor rails with gaps between the semiconductor rails; forming a tunneling dielectric layer over sides of the semiconductor rails and over the first contact layer in the gaps; forming a charge storage layer over the tunneling dielectric layer; forming a blocking dielectric layer over the charge storage layer; and forming a layer of control gate material over the blocking dielectric layer, wherein the layer of control gate material is located above the first contact layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification