Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices
First Claim
1. A One-Time Programmable (OTP) memory, comprising:
- a plurality of OTP cells, at least one of the cells comprising;
an OTP element including at least an interconnect coupled to a first supply voltage line;
a diode including at least a first active region and a second active region isolated from the first active region, where the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region providing a first terminal of the diode, the second active region providing a second terminal of the diode, both the first and second active regions residing in a common CMOS well or on an isolated substrate, the first active region coupled to the OTP element and the second active region coupled to a second supply voltage line,wherein the first and second active regions being fabricated from sources or drains of CMOS devices, andwherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change its logic state.
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Abstract
Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, metal, metal alloy, local interconnect, thermally isolated active region, CMOS gate, or combination thereof.
83 Citations
24 Claims
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1. A One-Time Programmable (OTP) memory, comprising:
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a plurality of OTP cells, at least one of the cells comprising; an OTP element including at least an interconnect coupled to a first supply voltage line; a diode including at least a first active region and a second active region isolated from the first active region, where the first active region having a first type of dopant and a second active region having a second type of dopant, the first active region providing a first terminal of the diode, the second active region providing a second terminal of the diode, both the first and second active regions residing in a common CMOS well or on an isolated substrate, the first active region coupled to the OTP element and the second active region coupled to a second supply voltage line, wherein the first and second active regions being fabricated from sources or drains of CMOS devices, and wherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change its logic state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An electronics system, comprising:
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a processor; and an One-Time Programmable (OTP) memory operatively connected to the processor, the OTP memory including a plurality of OTP cells, at least one of the cells comprising; an OTP element including at least an interconnect coupled to a first supply voltage line; a diode including at least a first active region and a second active region isolated from the first active region, where the first active region having a first type of dopant and the second region having a second type of dopant, the first active region providing a first terminal of the diode, the second active region providing a second terminal of the diode, both the first and second active regions residing in a common CMOS well or on an isolated substrate, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line, wherein the first and second active regions being fabricated from sources or drains of CMOS devices, and wherein the OTP element is configured to be programmable by applying voltages to the first and the second supply voltage lines to thereby change the resistance into a different logic state. - View Dependent Claims (20, 21)
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22. A method for operating an OTP memory comprises:
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providing a plurality of OTP cells, at least one of the OTP cells includes at least (i) an OTP element including at least one interconnect coupled to a first supply voltage line; and
(ii) a diode including at least a first active region and a second active region isolated from the first active region, where the first active region having a first type of dopant and the second region having a second type of dopant, the first active region providing a first terminal of the diode, the second active region providing a second terminal of the diode, both the first and second active regions being fabricated from sources or drains of CMOS devices and residing in a common CMOS well or on an isolated substrate, the first active region coupled to the OTP element, and the second active region coupled to a second supply voltage line; andone-time programming a logic state into at least one of the OTP cells by applying voltages to the first and the second voltage lines - View Dependent Claims (23, 24)
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Specification