FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS

• US 20120226724A1
• Filed: 02/29/2012
• Published: 09/06/2012
• Est. Priority Date: 03/01/2011
• Status: Active Grant

• Current Assignee: King Abdullah University of Science and Technology
• Original Assignee: King Abdullah University of Science and Technology
• Inventors: Salama, Khaled Nabil, Radwan, Ahmed Gomaa Ahmed, Zidan, Mohammed Affan
• Granted Patent: US 9,600,238 B2
• Time in Patent Office: Days
• US Class Current: 708/204
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G06F 7/586 using an integer algorithm, e.g. using linear congruential method
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/001 using chaotic signals
• CPC Class Codes: H04L 9/0656 Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher

Abstract

Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Claims

1. A digital circuit, comprising:

a plurality of digital state registers; and

one or more digital logic modules coupled to the plurality of digital state registers, each of the one or more digital logic modules configured to;

obtain a first value from two or more of the plurality of digital state registers;

determine a second value based upon the obtained first values and a chaotic differential equation; and

provide the second value to set a state of one of the two or more of the plurality of digital state registers.

2. The digital circuit of claim 1, wherein the one or more digital logic modules are configured to determine the corresponding second values according to a Runge-Kutta Fourth-order numerical solution to the chaotic differential equation.

3. The digital circuit of claim 1, wherein the one or more digital logic modules are configured to determine the corresponding second values according to a mid-point numerical solution to the chaotic differential equation.

4. The digital circuit of claim 1, wherein the one or more digital logic modules are configured to determine the corresponding second values according to an Euler numerical solution to the chaotic differential equation.

5. The digital circuit of claim 1, wherein the chaotic differential equation is a nonlinear jerk equation.

6. The digital circuit of claim 1, wherein the one or more digital logic modules are configured to determine the corresponding second values using shift operations without multiplication operations.

7. The digital circuit of claim 1, further comprising a post-processing module configured to discard a highest significant bit of at least one of the second values to generate a single random output.

8. The digital circuit of claim 7, wherein the post-processing module is further configured to discard a lowest significant bit of the at least one second values to generate the single random output.

9. The digital circuit of claim 1, further comprising a post-processing module configured to combine the state of the plurality of digital state registers to generate a single random output.

10. The digital circuit of claim 1, further configured to generate a chaos shift key (CSK).

11. An apparatus comprising a first digital circuit of claim 1 configured to provide second values with a length of 16-bits and a second digital circuit of claim 1 configured to provide second values with a length of 32-bits.

12. The apparatus of claim 11, wherein a second value of the first digital circuit and a corresponding second value of the second digital circuit are combined to generate a single random output.

13. A digital circuit, comprising:

a plurality of digital shift registers, each digital shift register configured to obtain an input and provide an output;

a plurality of digital logic modules, each digital logic module configured to obtain outputs from a subset of two or more of the plurality of digital shift registers and to provide the input for setting a state of at least one of the subset of digital shift registers, the plurality of digital logic modules each configured to provide the input according to a portion of a numeric solution to a chaotic differential equation; and

a digital clock configured to provide a digital clock signal for operating the plurality of digital shift registers.

14. The digital circuit of claim 13, wherein the plurality of digital shift registers are configured to provide the output to one or more of the plurality of digital logic modules on a first clock edge of the digital clock signal.

15. The digital circuit of claim 13, wherein the plurality of digital shift registers are configured to obtain the input from one of the plurality of digital logic modules on a second clock edge of the digital clock signal.

16. The digital circuit of claim 13, further comprising a digital post-processing module configured to generate a chaotic output in response to the inputs received by each of the plurality of digital shift registers.

17. The digital circuit of claim 16, wherein the post-processing module is configured to discard a highest significant bit of at least one of the second values to generate the chaotic output.

18. The digital circuit of claim 17, wherein the post-processing module is further configured to discard a lowest significant bit of at least one of the second values based upon a distribution of bits in the second values.

19. The digital circuit of claim 16, wherein the post-processing module is configured to combine the state of the plurality of digital state registers to generate a single random output.

20. The digital circuit of claim 13, wherein the plurality of digital logic modules do not include multipliers.

21. The digital circuit of claim 16, wherein the chaotic output is in a fixed-point number format.

22. The digital circuit of claim 13, further configured to generate an output that comprises a chaotic shift key (CSK).

23. A method, comprising:

receiving a clock signal having a first clock state and a second clock state;

obtaining first values from a subset of a plurality of digital state registers by each of a plurality of digital logic modules when the clock signal enters the first clock state;

transforming the first values in each of the plurality of digital logic modules into a corresponding second value based upon a numerical solution to one or more chaotic differential equations; and

writing the corresponding second values into a corresponding on of the plurality of digital state registers when the clock signal enters the second clock state.

24. The method of claim 23, further comprising providing at least one of the corresponding second values as a random number output.

25. The method of claim 24, further comprising discarding a highest significant bit of the at least one corresponding second value.

26. The method of claim 24, further comprising discarding a lowest significant bit of the at least one corresponding second value.

27. The method of claim 24, further comprising combining a plurality of the corresponding second values to form the random number output.

28. The method of claim 24, wherein the random number output comprises a fixed-point number.

29. The method of claim 23, wherein the one or more chaotic differential equations corresponds to a multi-scroll butterfly attractor.

30. The method of claim 29, further comprising providing a control signal to adjust parameters of the chaotic differential equations to modify the multi-scroll butterfly attractor.

31. The method of claim 23, wherein the one or more chaotic differential equations corresponds to a multidimensional multi-scroll attractor.