ADJUSTABLE PROGRAMMING SPEED FOR NAND MEMORY DEVICES

• US 20120226959A1
• Filed: 03/03/2011
• Published: 09/06/2012
• Est. Priority Date: 03/03/2011
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Goldman, Matthew, Faber, Robert W., Xie, Ningde, Khan, Jawad B.
• Granted Patent: US 8,595,597 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.

Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).

Claims

1. A system comprising:

a NAND memory device; and

a controller operatively coupled to the NAND memory device to

determine a storage fidelity of the NAND memory device during operation of the NAND memory device, and

adjust a programming speed characteristic of the NAND memory device based on the storage fidelity of the NAND memory device;

the NAND memory device to execute an error correction code (ECC) to correct bit errors that occur during a read operation of the NAND memory device, the ECC provisioned for end-of-life storage fidelity of the NAND memory device.

2. The system of claim 1, wherein determining the storage fidelity of the NAND memory device is based, at least in part, on a program/erase cycle count of the NAND memory device.

3. The system of claim 1, wherein determining the storage fidelity of the NAND memory device is based, at least in part, on a bit error rate of the NAND memory device.

4. The system of claim 1, wherein adjusting the programming speed characteristic of the NAND memory device is based, at least in part, on adjusting a voltage step size between programming voltage pulses applied to the NAND memory device.

5. The system of claim 1, wherein adjusting the programming speed characteristic of the NAND memory device is based, at least in part, on adjusting an exit criteria of programming operations to cause the NAND memory unit(s) to exit programming operations earlier.

6. The system of claim 1, wherein adjusting the programming speed characteristic of the NAND memory device comprises

determining a programming attribute of the NAND memory device;

and

accessing a lookup table that includes at least one index comprising a programming attribute value, and at least one corresponding value comprising a programming voltage characteristic value to be adjusted.

7. The system of claim 1, further comprising:

an antenna; and

radio frequency circuitry coupled to the antenna to receive signal data to be stored on the NAND memory device.

8. A method comprising:

determining a storage fidelity of a NAND memory device during operation of the NAND memory device, the NAND memory device to correct bit errors during a read operation via error correction code (ECC), the ECC provisioned for end-of-life storage fidelity of the NAND memory device; and

adjusting a programming speed characteristic of the NAND memory device based on the storage fidelity of the NAND memory device,

9. The method of claim 8, wherein determining the storage fidelity of the NAND memory device is based, at least in part, on a program/erase cycle count of the NAND memory device.

10. The method of claim 8, wherein determining the storage fidelity of the NAND memory device is based, at least in part, on a bit error rate of the NAND memory device.

11. The method of claim 8, wherein adjusting the programming speed characteristic of the NAND memory device is based, at least in part, on adjusting a voltage step size between programming voltage pulses applied to the NAND memory device.

12. The method of claim 8, wherein adjusting the programming speed characteristic of the NAND memory device is based, at least in part, on adjusting an exit criteria of programming operations to cause the NAND memory unit(s) to exit programming operations earlier.

13. The method of claim 8, wherein adjusting the programming speed characteristic of the NAND memory device comprises

determining a programming attribute of the NAND memory device;

and

accessing a lookup table that includes at least one index comprising a programming attribute value, and at least one corresponding value comprising a programming voltage characteristic value to be adjusted

14. A memory device comprising:

at least one NAND memory unit; and

a NAND memory unit controller to

determine a storage fidelity of the NAND memory unit(s) during operation of the NAND memory unit(s), and

adjust a programming speed characteristic of the NAND memory unit(s) based on the storage fidelity of the NAND memory unit(s);

the NAND memory unit(s) to execute an error correction code (ECC) to correct bit errors that occur during a read operation of the NAND memory unit(s), the ECC provisioned for end-of-life storage fidelity of the NAND memory unit(s).

15. The memory device of claim 14, wherein the determining the storage fidelity of the NAND memory unit(s) is based, at least in part, on a program/erase cycle count of the NAND memory unit(s).

16. The memory device of claim 14, wherein determining the storage fidelity of the NAND memory unit(s) is based, at least in part, on a bit error rate of the NAND memory unit(s).

17. The memory device of claim 14, wherein adjusting the programming speed characteristic of the NAND memory unit(s) is based, at least in part, on adjusting a voltage step size between programming voltage pulses applied to the NAND memory unit(s).

18. The memory device of claim 14, wherein adjusting the programming speed characteristic of the NAND memory unit(s) is based, at least in part, on adjusting an exit criteria of programming operations to cause the NAND memory unit(s) to exit programming operations earlier.

19. The memory device of claim 14, wherein adjusting the programming speed characteristic of the NAND memory unit(s) comprises

determining a programming attribute of the NAND memory unit(s);

and

accessing a lookup table that includes at least one index comprising a programming attribute value, and at least one corresponding value comprising a programming voltage characteristic value to be adjusted in order to adjust the programming speed characteristic of the NAND memory unit(s).