SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20120228606A1
• Filed: 03/07/2012
• Published: 09/13/2012
• Est. Priority Date: 03/11/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOEZUKA, Junichi, OHNO, Shinji, SATO, Yuichi, TAKAHASHI, Masahiro, KISHIDA, Hideyuki
• Granted Patent: US 9,184,296 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The semiconductor device includes an oxide semiconductor film having a first region and a pair of second regions facing each other with the first region provided therebetween, a gate insulating film over the oxide semiconductor film, and a first electrode overlapping with the first region, over the gate insulating film. The first region is a non-single-crystal oxide semiconductor region including a c-axis-aligned crystal portion. The pair of second regions is an oxide semiconductor region containing dopant and including a plurality of crystal portions.

Claims

1. A semiconductor device comprising:

an oxide semiconductor film including a first region, a second region, and a third region;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the gate insulating film, the gate electrode overlapping with the first region;

a first electrode electrically connected to the second region; and

a second electrode electrically connected to the third region,

wherein the first region is interposed between the second region and the third region,

wherein the first region comprises a first c-axis-aligned crystal portion,

wherein each of the second region and the third region comprises an oxide semiconductor region containing a dopant, and

wherein each of the second region and the third region comprises a plurality of crystal portions and a second c-axis-aligned crystal portion over the plurality of crystal portions.

2. The semiconductor device according to claim 1,

wherein the gate electrode serves as a mask for preventing the dopant from being contained in the first region.

3. The semiconductor device according to claim 1,

wherein the dopant is selected from the group consisting of phosphorus, arsenic, antimony, and boron.

4. The semiconductor device according to claim 1,

wherein a dopant concentration of the second region and the third region is higher than or equal to 5×

10¹⁸ cm<sup>−

3</sup> and lower than or equal to 1×

10²² cm<sup>−

3</sup>.

5. A semiconductor device comprising:

an oxide semiconductor film including a first region, a second region, a third region, a fourth region, and a fifth region;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the gate insulating film, the gate electrode overlapping with the first region;

a first electrode electrically connected to the second region; and

a second electrode electrically connected to the third region,

wherein the first region is interposed between the second region and the third region,

wherein the fourth region is interposed between the first region and the second region,

wherein the fifth region is interposed between the first region and the third region,

wherein the first region comprises a first c-axis-aligned crystal portion,

wherein each of the second region, the third region, the fourth region, and the fifth region comprises an oxide semiconductor region containing a dopant,

wherein a dopant concentration of the second region and the third region is higher than a dopant concentration of the fourth region and the fifth region, and

wherein each of the second region and the third region comprises a plurality of crystal portions and a second c-axis-aligned crystal portion over the plurality of crystal portions.

6. The semiconductor device according to claim 5,

wherein the gate electrode serves as a mask for preventing the dopant from being contained in the first region.

7. The semiconductor device according to claim 5,

wherein the dopant is selected from the group consisting of phosphorus, arsenic, antimony, and boron.

8. The semiconductor device according to claim 5,

wherein the dopant concentration of the second region and the third region is higher than or equal to 5×

10²⁰ cm<sup>−

3</sup> and lower than or equal to 1×

10²² cm<sup>−

3</sup>, and

wherein the dopant concentration of the fourth region and the fifth region is higher than or equal to 5×

10¹⁸ cm<sup>−

3</sup> and lower than 5×

10²¹ cm<sup>−

3</sup>.

9. The semiconductor device according to claim 5, further comprising a sidewall in contact with a side surface of the gate electrode,

wherein the sidewall is overlapped with the fourth region and the fifth region.

10. The semiconductor device according to claim 9,

wherein the gate insulating film is formed of an oxide insulator, and

wherein the sidewall is formed of a nitride insulator.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor film over a substrate, the oxide semiconductor film including a first c-axis aligned crystal portion;

forming a gate insulating film over the oxide semiconductor film;

forming a gate electrode over the oxide semiconductor film and the gate insulating film;

adding a dopant into the oxide semiconductor film excluding a first region overlapping with the gate electrode, whereby decreasing crystallinity of the oxide semiconductor film containing the dopant;

performing a heat treatment to form a second c-axis aligned crystal portion and a polycrystalline portion in the oxide semiconductor film containing the dopant, the second c-axis aligned crystal portion being over the polycrystalline portion; and

forming a first electrode and a second electrode over the gate insulating film.

12. The method according to claim 11, wherein the dopant is selected from the group consisting of phosphorus, arsenic, antimony, and boron.

13. The method according to claim 11,

wherein a dopant concentration of the oxide semiconductor film containing the dopant is higher than or equal to 5×

10¹⁸ cm<sup>−

3</sup> and lower than or equal to 1×

10²² cm<sup>−

3</sup>.

14. The method according to claim 11,

wherein crystallinity of the first region is improved by the heat treatment.

15. The method according to claim 11, further comprising the step of forming a sidewall to be in contact with a side surface of the gate electrode before adding the dopant,

wherein, in the oxide semiconductor film, a dopant concentration of a second region not overlapping with the sidewall is higher than a dopant concentration of a third region overlapping with the sidewall.

16. A semiconductor device comprising:

an oxide semiconductor film on an insulating surface, the oxide semiconductor film including a first region, a second region, and a third region;

a gate insulating film over the oxide semiconductor film;

a gate electrode over the gate insulating film, the gate electrode overlapping with the first region;

a first electrode electrically connected to the second region; and

a second electrode electrically connected to the third region,

wherein the first region is interposed between the second region and the third region,

wherein, in the first region, c-axes of crystals are aligned substantially perpendicularly to the insulating surface throughout a thickness of the oxide semiconductor film;

wherein each of the second region and the third region is added with an impurity element and comprises a first portion in contact with the insulating surface and a second portion over the first portion,

wherein the second portion has a polycrystalline oxide semiconductor, and

wherein, in the second portion, c-axes of crystals are aligned substantially perpendicularly to the insulating surface.

17. The semiconductor device according to claim 16,

wherein the gate electrode serves as a mask for preventing the impurity element from being contained in the first region.

18. The semiconductor device according to claim 16,

wherein the impurity element is selected from the group consisting of phosphorus, arsenic, antimony, and boron.

19. The semiconductor device according to claim 16,

wherein a concentration of the impurity element of the second region and the third region is higher than or equal to 5×

10¹⁸ cm<sup>−

3</sup> and lower than or equal to 1×

10²² cm<sup>−

3</sup>.