HIGH-YIELD FABRICATION OF LARGE-FORMAT SUBSTRATES WITH DISTRIBUTED, INDEPENDENT CONTROL ELEMENTS

• US 20120228669A1
• Filed: 09/16/2010
• Published: 09/13/2012
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Semprius, Inc.
• Inventors: Bower, Christopher, Menard, Etienne, Cok, Ronald S., Hamer, John
• Granted Patent: US 9,165,989 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: G01R 31/28 Testing of electronic circuits, e.g. by signal tracer EMC, EMP or similar testing of electronic circuits G01R31/002; testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers or computer components G06F11/00; checking static stores for correct operation G11C29/00 ; testing receivers or transmitters of transmission systems H04B17/00
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/129 Chiplets
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/70 Testing, e.g. accelerated lifetime tests

Abstract

A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s).

Claims

1. A method of assembling integrated circuit elements on a receiving substrate, the method comprising:

providing a wafer having a plurality of chiplets thereon;

determining that at least one of the chiplets on the wafer is defective;

selectively removing the at least one of the chiplets from the wafer leaving remaining ones of the chiplets on the wafer;

transferring the remaining ones of the chiplets from the wafer onto the receiving substrate to define at least one empty chiplet location on the receiving substrate; and

transferring at least one additional chiplet onto to the at least one empty chiplet location on the receiving substrate.

2. The method of claim 1, wherein determining that the at least one of the chiplets is defective comprises at least one of the following:

imaging the wafer to provide a wafer image and analyzing the wafer image to determine that the at least one of the chiplets is defective; and

electrically testing the plurality of chiplets on the wafer to determine that the at least one of the chiplets is defective.

3. The method of claim 1, wherein the wafer comprises a source wafer on which the plurality of chiplets were fabricated.

4. The method of claim 3, wherein the at least one additional chiplet is transferred onto the at least one empty chiplet location from the source wafer or from a different wafer.

5. The method of claim 1, wherein transferring the remaining ones of the chiplets onto the receiving substrate comprises:

printing the remaining ones of the chiplets onto the receiving substrate in parallel.

6. The method of claim 1, further comprising:

imaging the receiving substrate after transferring the remaining ones of the chiplets thereon to provide a substrate image; and

analyzing the substrate image to determine the at least one empty chiplet location.

7. The method of claim 1, further comprising:

imaging the receiving substrate after transferring the remaining ones of the chiplets or after transferring the at least one additional chiplet thereon to provide a substrate image; and

analyzing the substrate image to identify that at least one of the chiplets on the receiving substrate is mis-located or defective.

8. The method of claim 7, wherein the receiving substrate includes an adhesive layer thereon, and further comprising:

selectively removing the at least one of the chiplets identified as mis-located or defective from the receiving substrate before curing of the adhesive layer.

9. The method of claim 8, wherein selectively removing the at least one of the chiplets identified as mis-located or defective comprises:

providing a vacuum element operable to adhere the at least one of the chiplets identified as mis-located or defective by air pressure; and

mechanically removing the at least one of the chiplets identified as mis-located or defective using the vacuum element.

10. The method of claim 8, wherein selectively removing the at least one of the chiplets identified as mis-located or defective comprises:

providing a gripping element operable to grip and mechanically remove the at least one of the chiplets identified as mis-located or defective; and

mechanically removing the at least one of the chiplets identified as mis-located or defective using the gripping element.

11. The method of claim 1, further comprising:

forming electrical connections to the remaining ones of the chiplets and the at least one additional chiplet on the receiving substrate to define a plurality of interconnected chiplets on the receiving substrate; and

determining that at least one of the interconnected chiplets has a fault therein.

12. The method of claim 11, wherein determining that at least one of the interconnected chiplets includes the fault comprises at least one of the following:

imaging the receiving substrate to provide a substrate image and analyzing the substrate image to determine that the at least one of the interconnected chiplets has the fault; and

electrically testing the plurality of interconnected chiplets to determine that the at least one of the interconnected chiplets has the fault.

13. The method of claim 11, further comprising:

selectively removing the at least one of the interconnected chiplets having the fault therein from the receiving substrate to define at least one second empty chiplet location on the receiving substrate.

14. The method of claim 13, wherein selectively removing the at least one of the interconnected chiplets having the fault therein comprises:

removing material adhered to and surrounding the at least one of the interconnected chiplets having the fault therein; and

then

selectively removing the at least one of the interconnected chiplets having the fault therein.

15. The method of claim 14, wherein removing the material adhered to and surrounding the at least one of the interconnected chiplets having the fault therein comprises:

removing the material by laser ablation or by local chemical processing.

16. The method of claim 15, wherein the local chemical processing is a photolithographic process, and wherein removing the material by local chemical processing comprises:

coating a photosensitive resin over the receiving substrate; and

pattern-wise exposing and processing the photosensitive resin to form a locally chemically processable area over and around the at least one of the interconnected chiplets having the fault therein.

17. The method of claim 13, further comprising:

printing at least one second chiplet into the at least one second empty chiplet location on the receiving substrate; and

then

forming electrical interconnections to the at least one second chiplet.

18. The method of claim 11, further comprising:

printing a second chiplet on the at least one of the interconnected chiplets having the fault therein on the receiving substrate; and

then

forming electrical interconnections to the second chiplet.

19. The method of claim 18, further comprising:

providing an adhesive layer and/or a planarization layer on the at least one of the interconnected chiplets having the fault therein before printing the second chiplet thereon.

20. The method of claim 1, further comprising:

printing the at least one of the chiplets that was selectively removed from the wafer onto a different adhesive substrate.

21. The method of claim 7, further comprising:

providing a photosensitive adhesive layer on the receiving substrate prior to transferring the remaining ones of the chiplets to the receiving substrate; and

selectively exposing the adhesive layer at locations of the at least one of the chiplets identified as mis-located or defective to reduce adhesion between the receiving substrate and the at least one of the chiplets identified as mis-located or defective.

22. The method of claim 1, wherein the wafer includes a buried oxide layer having the plurality of chiplets thereon, and further comprising:

performing a release etch of portions of the buried oxide layer to separate portions of the chiplets from the wafer prior to selectively removing the at least one of the chiplets determined to be defective.

23. The method of claim 1, further comprising:

forming an OLED device on the receiving substrate,

wherein the OLED device is configured to be controlled by the printed chiplet(s).

24. An organic light emitting diode (OLED) device fabricated according to the method of claim 23.

25. A method of making a large-format substrate with distributed control elements comprises:

a) providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon;

then

b) imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective;

then

c) removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer;

then

d) printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s) on the substrate; and

then

e) printing additional chiplet(s) from the same or a different wafer in to the empty chiplet location(s) on the substrate.