SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120228700A1
• Filed: 09/20/2011
• Published: 09/13/2012
• Est. Priority Date: 03/09/2011
• Status: Abandoned Application

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Nakamura, Katsumi, Nishii, Akito
• Application Number:
  US13/237,309
• Publication Number:
  US 20120228700A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

Claims

1. A semiconductor device comprising:

an N-type drift layer;

a P-type anode layer on the N-type drift layer;

a trench penetrating the P-type anode layer;

a conductive substance embedded in the trench via an insulating film; and

an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

2. The semiconductor device according to claim 1, wherein the trench has a width which is equal to or below 1.2 μ

m.

3. The semiconductor device according to claim 1, wherein the N-type buffer layer has an impurity concentration which is equal to or below 1×

10¹⁷ cm<sup>−

3</sup>.

4. A method for manufacturing a semiconductor device comprising:

forming a P-type anode layer on a top surface of an N-type drift layer;

selectively forming an N-type cathode layer in a first region of an underside of the N-type drift layer; and

selectively forming a P-type cathode layer in a second region which is different from the first region of the underside of the N-type drift layer.

5. A semiconductor device comprising

an N-type drift layer;

a P-type anode layer on a part of the N-type drift layer;

an anode electrode connected to the P-type anode layer; and

an insulating film between an outer end of the P-type anode layer and the anode electrode,

wherein a length between the outer end of the P-type anode layer and an inner end of the insulating film is 100 μ

m or above.