SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

• US 20120228728A1
• Filed: 02/17/2012
• Published: 09/13/2012
• Est. Priority Date: 03/07/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: UEKI, Makoto, Inoue, Naoya, Hayashi, Yoshihiro
• Granted Patent: US 8,558,334 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Claims

1. A semiconductor device having a multilayered wiring layer formed over a substrate,

wherein a first layer contained in the multilayered wiring layer has:

a first interlayer insulating film; and

a plurality of first via holes buried in the first interlayer insulating film, and a plurality of first wirings buried in the first interlayer insulating film, connected with the first via holes, and exposed at the surface from the first interlayer insulating film, and

wherein a second layer contained in the multilayered wiring layer and situated just over has, in a first region,

an MRAM (magnetoresistive random access memory) having at least two first magnetization pinning layers in contact with the first wiring and insulated from each other,

a free magnetization layer overlapping the two first magnetization pinning layer in a plan view and connected with the first magnetization pinning layers,

a non-magnetic layer situated over the free magnetization layer, and

a second magnetization pinning layers situated over the non-magnetic layer;

a second interlayer insulating film covering the MRAM;

a second via hole buried in the second interlayer insulating film and connected with the second magnetization pinning layers; and

a second wiring buried in the second interlayer insulating film, connected with the second via hole, and exposed at the surface from the second interlayer insulating film.

2. The semiconductor device according to claim 1, wherein the height of the first layer and the height of the second layer are identical.

3. The semiconductor device according to claim 1, wherein the MRAM is not situated in a second region of the second layer, and the second interlayer insulating film formed over the first layer, a third via hole buried in the second interlayer insulating film and connected with the first wiring, and a third wiring buried in the second interlayer insulating film and connected with the third via hole are situated in the second region of the second layer.

4. The semiconductor device according to claim 1,

wherein the device further has a protective film covering the MRAM, and

wherein the protective film comprises an SiN film, an SiCN film, or a stacked film comprising the same.

5. The semiconductor device according to claim 4, wherein the protective film covers the upper surface and the lateral side of the MRAM.

6. The semiconductor device according to claim 4, wherein the protective film extends in the second region of the second layer and situated between the first layer and the second interlayer insulating film.

7. The semiconductor device according to claim 1, wherein the exposed surface of the first and the second wirings is covered with the metal cap film.

8. The semiconductor device according to claim 7, wherein the metal cap film covering the first wiring forms a portion of the MRAM.

9. The semiconductor device according to claim 1, wherein the first and the second interlayer insulating films comprises SiCOH.

10. The semiconductor device according to claim 9, wherein the first and the second interlayer insulating film comprising SiCOH have a C/Si ratio of 1 or more and less than 10.

11. A method of manufacturing a semiconductor device comprising:

a first step of forming a first interlayer insulating film over a substrate and then burying a plurality of first via holes and first wirings in the first interlayer insulating film so as to expose the first wirings thereby forming a first layer,

a second step of forming at least two first magnetization pinning layers electrically insulated from each other over the first wiring in a first region over the first layer,

a third step of completing an MRAM by forming a free magnetization layer overlapping the two first magnetization pinning layer in a plan view, and electrically connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layers situated over the non-magnetic layer,

a fourth step of forming a second interlayer insulating film covering the MRAM, and

a fifth step of burying a second via hole connected with the second magnetization pinning layer and a second wiring connected with the second via hole in the second interlayer insulating film.

12. The method of manufacturing a semiconductor device according to claim 11, further comprising:

a step of forming a protective film comprising an SiN film, a SiCN film, or a stacked film comprising the same so as to cover the MRAM after the third step and before the fourth step.

13. The method of manufacturing a semiconductor device according to claim 11,

wherein the second interlayer insulating film is formed over the second region over the first layer in the fourth step, and

wherein a third via hole connected with the first wiring and a third via hole connected with the third via hole are buried in the second interlayer insulating film in the second region by the identical processing of forming the second via hole and second wiring in the fifth step.

14. The method of manufacturing a semiconductor device according to claim 11, wherein the first and the second interlayer insulating 1 films are formed by plasma polymerizing reaction using a starting material having a cyclic organic silica structure represented by the following formula (I):

15. The method of manufacturing a semiconductor device according to claim 11, comprising:

a step of forming a mask film covering the first wiring exposed in the region where the MRAM is not formed after the first step and before the second step.

16. The method of manufacturing a semiconductor device according to claim 15, wherein the mask film comprises an SiN film or a SiCN film, or a stacked film formed by stacking the SiO₂ film and the SiCN film orderly from above.