TEST INTERFACE BOARD AND TEST SYSTEM INCLUDING THE SAME

• US 20120229159A1
• Filed: 02/24/2012
• Published: 09/13/2012
• Est. Priority Date: 03/08/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: WOO, Cheol-jong, KIM, Joon-yeon, CHO, Chang-hyun, KIM, Hyung-soon
• Application Number:
  US13/404,198
• Publication Number:
  US 20120229159A1
• Time in Patent Office: Days
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A test interface board includes a wiring group, a plurality of contact portions, and a control device. The wiring group includes a main wire operatively coupled to a channel of a tester, and a plurality of sub-wires operatively coupled to the main wire. The plurality of contact portions are operatively coupled to the plurality of sub-wires, and contact first electrodes of a plurality of semiconductor devices. The control device includes a plurality of switching devices operatively coupled to the plurality of sub-wires, a memory configured to store an identification number, and a controller configured to open and close the plurality of switching devices in response to a control signal corresponding to the identification number from among a plurality of control signals.

Claims

1. A test interface board, comprising:

a first wiring group comprising a first main wire operatively coupled to a first channel of a tester, and a plurality of first sub-wires operatively coupled to the first main wire;

a plurality of first contact portions operatively coupled to the plurality of first sub-wires, and contacting first electrodes of a plurality of semiconductor devices; and

a first control device comprising a plurality of first switching devices operatively coupled to the plurality of first sub-wires, a memory configured to store a first identification number, and a controller configured to open and close the plurality of first switching devices in response to a control signal corresponding to the first identification number from among a plurality of control signals.

2. The test interface board of claim 1, wherein the first channel is a power channel, and each of the plurality of first switching devices is one of a metal-oxide semiconductor (MOS) transistor and a relay.

3. The test interface board of claim 1, wherein the first channel is a data input/output channel, and each of the plurality of first switching devices is one of a bidirectional buffer, a metal-oxide semiconductor (MOS) transistor and a relay.

4. The test interface board of claim 1, wherein the memory is a programmable non-volatile memory.

5. The test interface board of claim 1, wherein the controller is a microcontroller.

6. The test interface board of claim 1, wherein the first control device is a multi-chip package.

7. The test interface board of claim 1, further comprising a circuit board, wherein the first wiring group is disposed on the circuit board, and the first control device is a semiconductor package mounted on the circuit board.

8. The test interface board of claim 1, wherein the plurality of semiconductor devices are each a semiconductor die, and the plurality of first contact portions are each a needle.

9. The test interface board of claim 1, wherein the plurality of semiconductor devices are each a semiconductor package, and the plurality of first contact portions are each a pogo pin.

10. The test interface board of claim 1, wherein the first channel is one of a plurality of first channels and the first wiring group is one of a plurality of wiring groups, wherein a number of the wiring groups is equal to a number of the first channels, and a number of the first contact portions and a number of the first switching devices are each greater than the number of the first channels.

11. The test interface board of claim 1, further comprising:

a second wiring group comprising a second main wire operatively coupled to a second channel of the tester, and a plurality of second sub-wires operatively coupled to the second main wire; and

a plurality of second contact portions operatively coupled to the plurality of second sub-wires, and contacting second electrodes of the plurality of semiconductor devices,

wherein the first control device further comprises a plurality of second switching devices operatively coupled to the plurality of second sub-wires, and the controller of the first control device is configured to open and close the plurality of first switching devices and the plurality of second switching devices in response to the control signal corresponding to the first identification number.

12. The test interface board of claim 11, wherein the first channel is a power channel and the plurality of first switching devices are each a MOS transistor or a relay, and

the second channel is a data input/output channel and the plurality of second switching devices are each one of a bidirectional buffer, a MOS transistor and a relay.

13. The test interface board of claim 1, further comprising:

a second wiring group comprising a second main wire operatively coupled to a second channel of the tester, and a plurality of sub-wires operatively coupled to the second main wire;

a plurality of second contact portions operatively coupled to the plurality of second sub-wires, and contacting second electrodes of the plurality of semiconductor devices; and

a second control device comprising a plurality of second switching devices operatively coupled to the plurality of second sub-wires, a memory configured to store a second identification number, and a controller configured to open and close the plurality of second switching devices in response to a control signal corresponding to the second identification number from among the plurality of control signals.

14. The test interface board of claim 13, wherein the plurality of control signals comprise identification data corresponding to the first identification number or the second identification number, and the identification data is transmitted to the first control device and the second control device in parallel.

15. A test system, comprising:

a tester;

a control signal generator configured to generate a plurality of control signals; and

a test interface board comprising;

a wiring group comprising a main wire operatively coupled to a channel of the tester, and a plurality of sub-wires operatively coupled to the main wire;

a plurality of contact portions operatively coupled to the plurality of sub-wires, and contacting electrodes of a plurality of semiconductor devices; and

a control device comprising a plurality of switching devices operatively coupled to the plurality of sub-wires, a memory configured to store an identification number, and a controller configured to open and close the plurality of switching devices in response to a control signal corresponding to the identification number from among the plurality of control signals.

16. The test system of claim 15, wherein the memory is a memory chip, the switching devices are disposed on a semiconductor chip, the controller is a microcontroller chip, and the control device is a multi-chip package comprising the memory chip, the semiconductor chip, and the microcontroller chip.

17-20. -20. (canceled)