FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE

• US 20120230085A1
• Filed: 09/28/2011
• Published: 09/13/2012
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kawai, Ken, Shimakawa, Kazuhiko, Katayama, Koji, Muraoka, Shunsaku
• Granted Patent: US 8,902,629 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.

Claims

1. A forming method of performing forming on a variable resistance nonvolatile memory element, by applying a forming voltage pulse to memory cells in each of which a variable resistance nonvolatile memory element is connected in series with a switch element, so as to change a resistance state of the variable resistance nonvolatile memory element from an initial state to an operable state, the initial state being a state where no voltage has yet been applied after manufacturing, and the operable state being a state where a resistance value of the variable resistance nonvolatile memory element is smaller than a resistance value of the variable resistance nonvolatile memory element in the initial state and the resistance state is changeable between a high resistance state and a low resistance state according to a polarity of a voltage pulse which is applied in a normal operation,

the variable resistance nonvolatile memory element including:

a first electrode;

a second electrode; and

a transition metal oxide layer provided between the first electrode and the second electrode,

the transition metal oxide layer including;

a first oxygen-deficient transition metal oxide layer connected to the first electrode; and

a second oxygen-deficient transition metal oxide layer in contact with the second electrode, the second oxygen-deficient transition metal oxide layer having an oxygen deficient degree smaller than an oxygen deficient degree of the first oxygen-deficient transition metal oxide layer,

the variable resistance nonvolatile memory element having;

in the normal operation, characteristics by which the resistance state is changed to the low resistance state when a positive voltage having a first writing voltage pulse which is equal to or higher than a first threshold voltage is applied to the first electrode with reference to the second electrode, and the resistance state is changed to the high resistance state when a positive voltage having a second writing voltage pulse which is equal to or higher than a second threshold voltage is applied to the second electrode with reference to the first electrode;

in the initial state, characteristics by which when a first forming voltage having an amplitude equal to or greater than a first absolute value is applied between the first electrode and the second electrode so that a cumulative time period during which the first forming voltage is applied exceeds a first predetermined time period, first forming occurs to change the resistance state of the variable resistance nonvolatile memory element from the initial state to a first operable state where the resistance state is changeable between the high resistance state and the low resistance state according to application of a normal operation voltage, and the first predetermined time period decreases as a current flowing in the variable resistance nonvolatile memory element increases in the application of the first forming voltage; and

in the first operable state after the first forming, characteristics by which when a second forming voltage is applied between the first electrode and the second electrode so that a cumulative time period during which the second forming voltage is applied exceeds a second predetermined time period, second forming occurs to change the resistance state of the variable resistance nonvolatile memory element from the first operable state to a second operable state where the resistance state is changeable to a low resistance state having a resistance value lower than a resistance value of the low resistance state in the first operable state, and

said forming method comprising;

applying the first forming voltage between the first electrode and the second electrode in the initial state, until the first forming occurs; and

applying the second forming voltage between the first electrode and the second electrode in the first operable state after the first forming, until the second forming occurs.

2. The forming method according to claim 1,

wherein said applying of the first forming voltage includes:

applying a first voltage having a first voltage pulse as the first forming voltage between the first electrode and the second electrode so as to change the resistance state of the variable resistance nonvolatile memory element from the initial state to the first operable state, the first voltage pulse having an amplitude equal to or greater than the first absolute value and having a first pulse width; and

determining whether or not the first forming successfully occurs by said applying of the first voltage having the first voltage pulse,

wherein said applying of the first voltage is further performed, when it is determined in said determining that the first forming does not successfully occur, and

in said further applying of the first voltage, the first voltage applied between the first electrode and the second electrode has a new first voltage pulse, the new first voltage pulse having an amplitude equal to or greater than the first absolute value, and the new first voltage pulse having a pulse width longer than a pulse width of the first voltage pulse in said applying of the first voltage which is performed immediately prior to said further applying of the first voltage, and

said applying of the second forming voltage includes;

applying a second voltage having a second voltage pulse as the second forming voltage between the first electrode and the second electrode so as to change the resistance state of the variable resistance nonvolatile memory element from the first operable state achieved by the first forming to the second operable state; and

determining whether or not the second forming successfully occurs by said applying of the second voltage having the second voltage pulse,

wherein said applying of the second voltage is further performed, when it is determined in said determining that the second forming does not successfully occur.

3. The forming method according to claim 2,

wherein, in said determining whether or not the first forming successfully occurs, it is determined whether or not the first forming successfully occurs, by (i) applying a positive voltage having a third writing voltage pulse which is equal to or higher than the first threshold voltage to the first electrode with reference to the second electrode, and (ii) determining, after said applying of the positive voltage having the third writing voltage pulse, whether or not the variable resistance nonvolatile memory element is in the low resistance state having the resistance value lower than the resistance value in the initial state.

4. The forming method according to claim 2,

wherein, in said determining whether or not the second forming successfully occurs, it is determined whether or not the second forming successfully occurs, by (i) applying a positive voltage having a fourth writing voltage pulse which is equal to or higher than the first threshold voltage to the first electrode with reference to the second electrode and (ii) determining, after said applying of the positive voltage having the fourth writing voltage pulse, whether or not the variable resistance nonvolatile memory element is in the low resistance state to which the resistance state of the variable resistance nonvolatile memory element is changeable only from the second operable state.

5. The forming method according to claim 2,

wherein said determining whether or not the first forming successfully occurs and said applying of the first voltage having the first voltage pulse are repeated, until it is determined in said determining that the first forming successfully occurs.

6. The forming method according to claim 2,

wherein said determining whether or not the second forming successfully occurs and said applying of the second voltage having the second voltage pulse are repeated, until it is determined in said determining that the second forming successfully occurs.

7. The forming method according to claim 4,

wherein a pulse width of one of the third writing voltage pulse and the fourth writing voltage pulse is equal to the pulse width of the first writing voltage pulse.

8. The forming method according to claim 1,

wherein a material of the first electrode is different from a material of the second electrode, and

the second electrode comprises one of:

iridium (Ir); and

an alloy of Ir and platinum (Pt).

9. The forming method according to claim 1,

wherein the first oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_x, and

the second oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_y, where x<

y.

10. A variable resistance nonvolatile memory device including memory cells in each of which a variable resistance nonvolatile memory element is connected in series to a switch element,

said variable resistance nonvolatile memory element including:

a first electrode;

a second electrode; and

a transition metal oxide layer provided between said first electrode and said second electrode,

said transition metal oxide layer including;

a first oxygen-deficient transition metal oxide layer connected to said first electrode; and

a second oxygen-deficient transition metal oxide layer in contact with said second electrode, said second oxygen-deficient transition metal oxide layer having a oxygen deficient degree smaller than an oxygen deficient degree of said first oxygen-deficient transition metal oxide layer,

said variable resistance nonvolatile memory element having;

characteristics by which the resistance state is changed to a low resistance state when a positive voltage having a first writing voltage pulse which is equal to or higher than a first threshold voltage is applied to said first electrode with reference to said second electrode, and the resistance state is changed to a high resistance state when a positive voltage having a second writing voltage pulse which is equal to or higher than a second threshold voltage is applied to said second electrode with reference to said first electrode;

in the initial state, characteristics by which when a first forming voltage having an amplitude equal to or greater than a first absolute value is applied between said first electrode and said second electrode so that a cumulative time period during which the first forming voltage is applied exceeds a first predetermined time period, first forming occurs to change the resistance state of said variable resistance nonvolatile memory element from the initial state to a first operable state where the resistance state is changeable between the high resistance state and the low resistance state according to application of a normal operation voltage, and the first predetermined time period decreases as a current flowing in said variable resistance nonvolatile memory element increases in the application of the first forming voltage; and

in the first operable state after the first forming, characteristics by which when a second forming voltage is applied between said first electrode and said second electrode so that a cumulative time period during which the second forming voltage is applied exceeds a second predetermined time period, second forming occurs to change the resistance state of said variable resistance nonvolatile memory element from the first operable state to a second operable state where the resistance state is changeable to a low resistance state having a resistance value lower than a resistance value of the low resistance state in the first operable state,

said variable resistance nonvolatile memory device comprising;

a memory cell array including said memory cells in each of which said variable resistance nonvolatile memory element is connected in series to said switch element;

a selection unit configured to select at least one memory cell from said memory cell array;

a sense amplifier which determines whether said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit is in the high resistance state or in the low resistance state;

an automatic forming unit including;

a forming voltage pulse generation unit configured to generate a forming voltage having a forming voltage pulse so as to be applied to said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit, the forming voltage pulse having an amplitude equal to or higher than the first absolute value;

a forming success detection unit configured to detect whether or not said variable resistance nonvolatile memory element is in a resistance state that is a state achieved by success of the first forming to have a resistance value lower than a resistance value in the initial state; and

a forming success signal generation unit configured to eventually generate a forming success signal when a predetermined time period has passed since the detection of the success of the first forming by said forming success detection unit; and

an automatic forming control unit configured to (i) automatically and sequentially generate address signals, and (ii) control, according to the address signals, said automatic forming unit to cause the first forming and the second forming in said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit;

wherein said automatic forming unit is configured to (i) apply the forming voltage of the forming voltage pulse as the first forming pulse between said first electrode and said second electrode to cause one pulse application to occur the first forming and the second forming in said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit, the forming voltage pulse having an amplitude greater than an amplitude of a predetermined voltage, (ii) when said forming success detection unit detects that said variable resistance nonvolatile memory element is changed to the resistance state achieved by the success of the first forming, (ii-1) generate the forming success signal after the predetermined time period has passed since the detection, while applying the forming voltage having the forming voltage pulse as the second forming pulse, (ii-2) stop the application of the forming voltage having the forming voltage pulse, and (ii-3) terminate the forming on the at least one memory cell selected by said selection unit.

11. The variable resistance nonvolatile memory device according to claim 10,

wherein in the application of the forming voltage having the forming voltage pulse, a flow-able amount of a current is limited not to exceed a predetermined current amount.

12. The variable resistance nonvolatile memory device according to claim 10,

wherein said forming success signal generation unit includes:

a shift register circuit having n stages, where n is an integer of 2 or more; and

an AND circuit which receives all outputs of said shift register circuit at the n stages.

18. The variable resistance nonvolatile memory device according to claim 10,

wherein a material of said first electrode is different from a material of said second electrode, and

said second electrode comprises one of:

iridium (Ir); and

an alloy of Ir and platinum (Pt).

19. The variable resistance nonvolatile memory device according to claim 10,

wherein said first oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_x, and

said second oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_y, where x<

y.

13. A variable resistance nonvolatile memory device including memory cells in each of which a variable resistance nonvolatile memory element is connected in series to a switch element,

said variable resistance nonvolatile memory element including:

a first electrode;

a second electrode; and

a transition metal oxide layer provided between said first electrode and said second electrode,

said transition metal oxide layer including;

a first oxygen-deficient transition metal oxide layer connected to said first electrode; and

a second oxygen-deficient transition metal oxide layer in contact with said second electrode, said second oxygen-deficient transition metal oxide layer having a oxygen deficient degree smaller than an oxygen deficient degree of said first oxygen-deficient transition metal oxide layer,

said variable resistance nonvolatile memory element having;

characteristics by which the resistance state is changed to a low resistance state when a positive voltage having a first writing voltage pulse which is equal to or higher than a first threshold voltage is applied to said first electrode with reference to said second electrode, and the resistance state is changed to a high resistance state when a positive voltage having a second writing voltage pulse which is equal to or higher than a second threshold voltage is applied to said second electrode with reference to said first electrode;

in the initial state, characteristics by which when a first forming voltage having an amplitude equal to or greater than a first absolute value is applied between said first electrode and said second electrode so that a cumulative time period during which the first forming voltage is applied exceeds a first predetermined time period, first forming occurs to change the resistance state of said variable resistance nonvolatile memory element from the initial state to a first operable state where the resistance state is changeable between the high resistance state and the resistance state according to application of a normal operation voltage, and the first predetermined time period decreases as a current flowing in said variable resistance nonvolatile memory element increases in the application of the first forming voltage; and

in the first operable state after the first forming, characteristics by which when a second forming voltage is applied between said first electrode and said second electrode so that a cumulative time period during which the second forming voltage is applied exceeds a second predetermined time period, second forming occurs to change the resistance state of said variable resistance nonvolatile memory element from the first operable state to a second operable state where the resistance state is changeable to a low resistance state having a resistance value lower than a resistance value of the low resistance state in the first operable state, and

said variable resistance nonvolatile memory device comprising;

a memory cell array including said memory cells in each of which said variable resistance nonvolatile memory element is connected in series to said switch element;

a selection unit configured to select at least one memory cell from said memory cell array;

a forming power source which generates a forming voltage to cause forming in said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit;

a writing power source which generates the positive voltage having the first writing voltage pulse and the positive voltage having the second writing voltage pulse to be applied to said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit;

a variable-pulse-width writing voltage pulse generation unit configured to generate a variable-pulse-width writing voltage pulse to change the resistance state of said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit to a desired state, when one of the forming and writing is to be performed on the variable resistance nonvolatile memory element, the variable-pulse-width writing voltage pulse having a variable pulse width;

a first forming determination unit configured to determine whether or not said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit is in the resistance state achieved by success of the first forming to have a resistance value lower than a resistance value in the initial state;

a second forming determination unit configured to determine whether or not said variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit is in the low resistance state changeable only in the second operable state; and

a sense amplifier which determines whether the variable resistance nonvolatile memory element included in the at least one memory cell selected by said selection unit is in a high resistance state or in a low resistance state,

wherein said variable-pulse-width writing voltage pulse generation unit configured to;

(i-1) apply a first voltage having a first voltage pulse between said first electrode and said second electrode to cause the first forming in said variable resistance nonvolatile memory element, the first voltage pulse having an amplitude equal to or greater than the first absolute value and having a first pulse width, and (i-2) when said first forming determination unit determines that said variable resistance nonvolatile memory element after the application of the first voltage having the first voltage pulse is not in the resistance state achieved by success of the first forming, apply a second voltage having a second voltage pulse between said first electrode and said second electrode, the second voltage pulse having an amplitude equal to or greater than the first absolute value and having a pulse width longer than the first pulse width; and

(ii-1) apply an additional voltage having an additional voltage pulse with a third voltage width between the first electrode and the second electrode to cause the second forming in said variable resistance nonvolatile memory element, and (i-2) when said second forming determination unit determines that said variable resistance nonvolatile memory element is not in the low resistance state changeable only in the second operable state after the application of the additional voltage having the additional voltage pulse, further apply the additional voltage having the additional voltage pulse with the third pulse width between said first electrode and said second electrode.

14. The variable resistance nonvolatile memory device according to claim 13,

wherein said second forming determination unit is configured to determine whether or not said variable resistance nonvolatile memory element is in the low resistance state changeable only in the second operable state, after a positive voltage having a third writing voltage pulse equal to or higher than the first threshold voltage is applied to said first electrode with reference to said second electrode for the at least one memory cell.

15. The variable resistance nonvolatile memory device according to claim 13,

wherein the determination by said first forming determination unit and the application of the second voltage having the second voltage pulse by said variable-pulse-width writing voltage pulse generation unit are repeated until said first forming determination unit determines that said variable resistance nonvolatile memory element is in a resistance state lower than an initial low resistance state in the initial state, and

said variable-pulse-width writing voltage pulse generation unit is configured to generate a voltage having a first forming voltage pulse in the application of the second voltage having the second voltage pulse, the first forming voltage pulse having a pulse width gradually increased from a short pulse width.

16. The variable resistance nonvolatile memory device according to claim 13,

wherein the determination by said second forming determination unit and the application of the additional voltage having the additional voltage pulse by said variable-pulse-width writing voltage pulse generation unit are repeated until said second forming determination unit determines that said variable resistance nonvolatile memory element is in the low resistance state changeable only in the second operable state, and

said variable-pulse-width writing voltage pulse generation unit configured to generate a voltage having a second forming voltage pulse in the application of the additional voltage having the additional voltage pulse, the second forming voltage pulse having a predetermined fixed pulse width.

17. The variable resistance nonvolatile memory device according to claim 14,

wherein a pulse width of the third writing voltage pulse is equal to a pulse width for a normal writing operation.

20. The variable resistance nonvolatile memory device according to claim 13,

wherein a material of said first electrode is different from a material of said second electrode, and

said second electrode comprises one of:

iridium (Ir); and

an alloy of Ir and platinum (Pt).

21. The variable resistance nonvolatile memory device according to claim 13,

wherein said first oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_x, and

said second oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_y, where x<

y.