Variable Architecture for Random Number Generators

• US 20120233232A1
• Filed: 03/09/2011
• Published: 09/13/2012
• Est. Priority Date: 03/09/2011
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Inventors: Vergnes, Alain, Pean, Guillaume, Schumacher, Frédéric
• Granted Patent: US 8,805,906 B2
• Time in Patent Office: Days
• US Class Current: 708/251
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data.

Claims

1. A system comprising:

one or more inputs configured for receiving one or more digital values that are substantially constant and unique to the system; and

one or more circuits coupled to the one or more inputs, the one or more circuits including one or more digital circuit elements that are configurable by the one or more received digital values to produce one or more pseudo random digital values.

2. The system of claim 1, where the one or more inputs are fuse bits.

3. The system of claim 2, where the fuse bits carry a calibration of one or more analog cells embedded in the system.

4. The system of claim 2, where the fuse bits carry a unique identifier associated with the system.

5. The system of claim 1, where the one or more inputs are driven by input pads of the system.

6. The system of claim 1, where the one or more inputs are driven by outputs of flash memory embedded in the system.

7. The system of claim 6, where the outputs of flash memory carry a calibration of analog cells embedded in the system.

8. The system of claim 6, where the outputs of flash memory carry a unique identifier associated with the system

9. The system of claim 1, where the one or more digital circuit elements are included in a ring oscillator and configured to modify propagation delay in the ring oscillator.

10. The system of claim 9, where the propagation delay is modified by adding more delay elements in the ring oscillator.

11. The system of claim 10, where the one or more digital circuit elements are included in a linear feedback shift register coupled to the ring oscillator and configured to modify a polynomial describing a linear function of the linear feedback shift register.

12. The system of claim 11, where the one or more digital logic elements are included in combinational mixer architecture coupled to the linear feedback shift register and configured to invert at least a part of a random output signal of the combinational mixer.

13. The system of claim 1, where the system is a microcontroller.

14. The system of claim 13, where the one or more digital inputs are driven by a programmable register in the microcontroller.

15. The system of claim 14, where the programmable register is programmed with a value previously read from non-volatile registers of the system.

16. A method comprising:

receiving in a microcontroller data unique to the microcontroller;

adjusting one or more digital circuits of a pseudo random number generator in the microcontroller based on the unique data; and

generating a pseudo random sequence using the adjusted one or more digital circuits.

17. The method of claim 16, where receiving data unique to the microcontroller further comprises:

receiving at least one of fuse bits or a unique identifier of the microcontroller.

18. The method of claim 16, where adjusting one or more digital circuits of a pseudo random number generator in the microcontroller further comprises:

adjusting a propagation delay of a ring oscillator in the pseudo random number generator.

19. The method of claim 18, where adjusting one or more digit circuits of a pseudo random number generator in the microcontroller further comprises:

modifying a polynomial describing a linear function of a linear feedback shift register coupled to the ring oscillator.

20. The method of claim 19, where adjusting one or more digit circuits of a pseudo random number generator in the microcontroller further comprises:

inverting at least a part of a random output signal of a combinational mixer coupled to the linear feedback shift register.

21. The method of claim 16, where receiving in a microcontroller data unique to the microcontroller further comprises:

programming a programmable register in the microcontroller with unique data previously read from a non-volatile register of the microcontroller; and

retrieving the unique data from the programmable register.