REMAPPING FOR MEMORY WEAR LEVELING

• US 20120233381A1
• Filed: 11/30/2009
• Published: 09/13/2012
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Tucek, Joseph A., Anderson, Eric A.
• Granted Patent: US 8,745,357 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A method and a corresponding apparatus provide for remapping for wear leveling of a memory (10). The method (300) is implemented as logic and includes the steps of receiving (305) a memory operation, the memory operation including a logical memory address (20); dividing the logical address into a logical block address portion (22), a logical line address portion (24), and a logical subline address portion (26); translating (315) the logical block address portion into a physical block address (23); selecting (320) a line remap key (33); applying the line remap key to the logical line address portion to produce a physical line address (25); producing (335) a physical subline address portion (26); and combining (340) the physical block, line, and subline address portions to produce a physical address (28) for the memory operation.

Claims

1. A method (300) for remapping for wear leveling of a memory (10), the method implemented as logic, comprising:

receiving (305) a memory operation, the memory operation including a logical memory address (20);

dividing (310) the logical address into a logical block address portion (22), a logical line address portion (24), and a logical subline address portion (26);

performing a block remapping, producing a physical block address (23);

selecting (320) a line remap key (33) to perform a line remapping within a block of a same block size that the block remapping is performed;

applying (320) the line remap key to the logical line address portion to produce a physical line address (25);

producing (335) a physical subline address (26); and

combining the physical block, line, and subline addresses to produce a physical, address (28) for the memory operation.

2. The method of claim 1, wherein performing the block remapping comprises translating (315) the logical block address portion into the physical block address (23).

3. The method of claim 1, wherein selecting a line remap key comprises applying the logical block address portion (22) to a lute remap table (35).

4. The method of claim 1, wherein selecting a line remap key comprises applying the physical block address (23) to a line remap table.

5. The method of claim 1, wherein applying the line remap key to the logical line address portion to produce a physical line address comprises applying the line remap key (33) to a line remap function (34), and wherein the line remap key (33) is varied.

6. The method of claim 5, wherein the line remap function (34) is one of a swizzle function, a Bob Jenkins hash, addition modulo, multiplication, and a cryptographic function.

7. The method of claim 6, wherein the logic for remapping is provided on a same chip as the memory (10).

8. The method of claim 5, wherein the line remap function (34) is one of a keyed bit swizzle function, an XOR function, and a multiplication by an odd key modulo an address size.

9. The method of claim 1, wherein the logic for remapping is provided on a first chip, and the memory (10) is provided on a second chip.

10. The method of claim 9, wherein the memory is a memory type having a limited lifetime caused by wear out, including one of a flash memory, a memristor, and a phase-change memory.

11. A remapping apparatus, used for wear leveling and implemented as logic, wherein a memory (10) receives translated physical addresses for certain memory operations, the translated physical addresses providing a leveling of use of areas of the memory, comprising:

an address parsing function that divides a logical address (20) into logical block (22), line (24), and subline (26) address portions;

a block remap table (32) that performs a block remapping to produce a physical block address (23);

a line remap table (35) that provides a line remap key (33) to perform a line remapping within a block of a same block size that the block remapping is performed;

a line remap function (34) that receives the key (33) and produces a physical line address (25);

a subline translation device that produces a physical subline address (26) based on the logical subline address portion; and

a physical address function that produces a physical address (28) based on the physical block, line, and subline addresses, wherein the physical address designates the location in the memory for a memory operation.

12. The apparatus of claim 11, wherein the block remap table (32) performs the block remapping by translating the logical block address portion into the physical block address (23).

13. The apparatus of claim 11, wherein the line remap key is determined by applying the logical block address portion to the line remap table,

14. The apparatus of claim 11, wherein the line remap key is determined by applying the physical block address to the line remap table.

15. The apparatus of claim 11, wherein the line remap function is one of a swizzle function, a Bob Jenkins hash, addition modulo, multiplication, and a cryptographic function.

16. The apparatus of claim 15, wherein the logic for remapping is provided on a same chip as the memory (10).

17. The apparatus of claim 11, wherein the fine remap function is one of a keyed bit swizzle function, an XOR function, and a multiplication by an odd key modulo an address size.

18. The apparatus of claim 11, wherein the block remap table comprises a counter to maintain a count of updates of physical memory blocks.

19. The apparatus of claim 11, wherein the logic for remapping is provided on a first chip, and the memory (10) is provided on a second chip.