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Scheduling Workloads Based On Cache Asymmetry

  • US 20120233393A1
  • Filed: 03/08/2011
  • Published: 09/13/2012
  • Est. Priority Date: 03/08/2011
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a processor including a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache, the first and second caches asymmetric caches of a common cache level, wherein a scheduler is to schedule a plurality of threads to the first and second cores based at least in part on cache performance information obtained during a training phase of the plurality of threads on the asymmetric caches.

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