Protecting Large Objects Within an Advanced Synchronization Facility

• US 20120233411A1
• Filed: 03/07/2011
• Published: 09/13/2012
• Est. Priority Date: 03/07/2011
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pohlack, Martin T., Hohmuth, Michael P., Diestelhorst, Stephan, Christie, David S., Chung, Jaewoong
• Granted Patent: US 8,612,694 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.

Claims

1. An apparatus comprising:

a processor coupleable to a shared memory that is shared by one or more other processors, wherein the processor is configured to execute a section of code that includes a plurality of memory access operations to the shared memory; and

the processor comprising a large object protection module, the large object protection module configured to allow protection of areas larger than memory lines by monitoring accessed and dirty bits in one or more page tables.

2. The apparatus of claim 1 wherein:

the processor comprises first and second associative structures, the second associative structure having a different granularity than the first associative structure so as to at least partially filter out false positives for conflicts.

3. The apparatus of claim 2 wherein:

the second associative structure is of a size such that the set associative structure specifies a region in which conflicting cache lines lie.

4. The apparatus of claim 3 wherein:

if entries within the region are evicted from the second associative structure, the large object protection module is configured to track an entire index to filter out false positives depending on a granularity and a number of indices present.

5. The apparatus of claim 3 wherein:

the second associative structure is configured to correspond to a structure of translation look aside buffer (TLB).

6. A multiprocessor computer system comprising:

a shared memory; and

a plurality of processors coupled to the shared memory, each of the plurality of processors being configured to execute a section of code, the section of code comprising a plurality of memory access operations to the shared memory and each of the plurality of processors comprising a large object protection module, the large object protection module configured to allow protection of areas larger than memory lines by monitoring accessed and dirty bits in one or more page tables.

7. The multiprocessor computer system of claim 6 wherein:

each of the plurality of processors comprises first and second associative structures, the second associative structure having a different granularity than the first associative structure so as to at least partially filter out false positives for conflicts.

8. The multiprocessor computer system of claim 7 wherein:

the second associative structure is of a size such that the structure second sect associated structure exactly specifies a region in which conflicting cache lines lie.

9. The multiprocessor computer system of claim 8 wherein:

if entries within the region are evicted from the second associative structure, the large object protection module is configured to track an entire index to filter out false positives depending on a granularity and a number of indices present.

10. The multiprocessor computer system of claim 8 wherein:

the second associative structure is configured to correspond to a structure of translation look aside buffer (TLB).

11. In a system comprising a memory shared among a plurality of processors, a method comprising:

executing a section of code via one of the plurality of processors, the section of code comprising a plurality of memory access operations to the shared memory; and

monitoring accessed and dirty bits in a page table so as to provide protection of areas larger than memory lines.

12. The method of claim 11 further comprising:

providing each of the plurality of processors with first and second associative structures, the second associative structure having a different granularity than the first associative structure so as to at least partially filter out false positives for conflicts.

13. The method of claim 12 wherein:

the second associative structure is of a size such that the second associative structure exactly specifies a region in which conflicting cache lines lie.

14. The method of claim 13 wherein:

if entries within the region are evicted from the second associative structure, then tracking an entire index to filter out false positives depending on a granularity and a number of indices present.

15. The method of claim 13 wherein:

the second associative structure is configured to correspond to a structure of translation look aside buffer (TLB).

16. A computer readable medium comprising code stored therein, said code being executable by a processor to fabricate a multiprocessor computer system, said multiprocessor computer system comprising:

a shared memory;

a plurality of processors coupled to the shared memory, each of the plurality of processors being configured to execute a section of code, the section of code comprising a plurality of memory access operations to the shared memory and comprising a large object protection module, the large object protection module allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables.

17. The computer readable medium of claim 16 wherein:

each of the plurality of processors comprise first and second associative structures, the second associative structure having a different granularity than the first associative structure so as to at least partially filter out false positives for conflicts.

18. The computer readable medium of claim 17 wherein:

the second associative structure is of a size such that the second associative structure exactly specifies a region in which conflicting cache lines lie.

19. The computer readable medium of claim 18 wherein:

if entries within the region are evicted from the second associative structure, the large object protection module is configured to track an entire index to filter out false positives depending on a granularity and a number of indices present.

20. The computer readable medium of claim 18 wherein:

the second associative structure is configured to correspond to a structure of translation look aside buffer (TLB).