MASK LEVEL REDUCTION FOR MOFET

• US 20120235138A1
• Filed: 05/26/2012
• Published: 09/20/2012
• Est. Priority Date: 11/04/2009
• Status: Active Grant

• Current Assignee: Fantasy Shine Limited
• Original Assignee: CBRITE Inc.
• Inventors: Shieh, Chan-Long, Yu, Gang, Foong, Fatt, Lee, Liu-Chung
• Granted Patent: US 9,129,868 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

Claims

1. A method of fabricating a thin film transistor and in-plane-switch LCD electrodes with reduced masking operations, the method comprising the steps of:

providing a substrate with a surface;

patterning gate metal on the surface of the substrate to define a thin film transistor gate;

forming a layer of gate dielectric over the gate and surrounding substrate surface;

depositing a layer of semiconducting metal oxide on the layer of gate dielectric;

patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;

depositing at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area;

etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals, and etching through the semiconducting metal oxide layer in areas not covered by the source/drain metal layer;

patterning an organic dielectric material on the thin film transistor source and drain terminals and at surrounding area of the first electrode for the in-plane-switch;

using the patterned organic dielectric material, etching through the source/drain metal layer in the in-plane-switch area to expose the semiconducting metal oxide and define a first electrode for an in-plane-switch;

depositing a passivation layer on the patterned organic dielectric material and the first electrode for the in-plane-switch; and

patterning a layer of transparent electrically conductive material on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode.

2. A method as claimed in claim 1 wherein the second electrode for the in-plane-switch includes multiple interconnected, spaced apart fingers.

3. A method as claimed in claim 1 wherein the step of depositing the layer of semiconducting metal oxide includes depositing an amorphous metal oxide.

4. A method as claimed in claim 1 wherein the step of patterning the layer of transparent electrically conductive material includes patterning a layer of one of ITO, IZO, AZO, In₂O₃ and combinations thereof.

5. A method as claimed in claim 1 wherein the step of depositing at least the source/drain metal layer includes depositing a layer of transparent metal oxide conductor on the organic dielectric material.

6. A method as claimed in claim 5 wherein the step of depositing the layer of transparent metal oxide conductor includes depositing one of ITO, IZO, AZO, In₂O₃ and combinations thereof.

7. A method as claimed in claim 5 wherein the step of depositing at least the source/drain metal layer includes depositing a barrier metal layer on the transparent metal oxide conductor and depositing the source/drain metal layer on the barrier metal layer.

8. A method as claimed in claim 7 wherein the step of etching through the source/drain metal layer in the in-plane-switch area includes etching through the barrier layer but not etching through the layer of transparent metal oxide conductor.

9. A method as claimed in claim 7 wherein the step of depositing the barrier metal layer includes depositing one of Mo, W, Cr, and Ni.

22. A method as claimed in claim 1 wherein the substrate is one of flexible and rigid.

10. A method of fabricating a thin film transistor and in-plane-switch LCD electrodes with six patterning/masking operations, the method comprising the steps of:

providing a substrate with a surface;

a first patterning/masking operation including patterning gate metal on the surface of the substrate to define a thin film transistor gate and contacts/leads for external electrical connections to the thin film transistor and in-plane-switch;

forming a layer of gate dielectric over the gate and the contacts/leads and surrounding substrate surface;

depositing a layer of semiconducting metal oxide on the layer of gate dielectric;

a second patterning/masking operation including patterning a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;

depositing at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area;

a third patterning/masking operation including etching through the source/drain metal layer to the channel protection layer above the gate to separate the source/drain metal layer into thin film transistor source and drain terminals, and etching through the semiconducting metal oxide layer over the contacts/leads;

a fourth patterning/masking operation including patterning an organic dielectric material on the thin film transistor source and drain terminals and at an opposed side of the first electrode for the in-plane-switch;

using the patterned organic dielectric material, etching through the source/drain metal layer in the in-plane-switch area to expose the semiconducting metal oxide and define a first electrode for an in-plane-switch;

depositing a passivation layer on the patterned organic dielectric material and the first electrode for the in-plane-switch;

a fifth patterning/masking operation including etching vias through the passivation layer and the layer of gate dielectric into communication with the contacts/leads; and

a sixth patterning/masking operation including patterning a layer of transparent electrically conductive material on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode and through the vias into contact with the contacts/leads.

11. A method as claimed in claim 10 wherein the second electrode for the in-plane-switch includes multiple interconnected, spaced apart fingers.

12. A method as claimed in claim 10 wherein the step of depositing the layer of semiconducting metal oxide includes depositing an amorphous metal oxide.

13. A method as claimed in claim 10 wherein the step of patterning the layer of transparent electrically conductive material includes patterning a layer of one of ITO, IZO, AZO, In₂O₃ and combinations thereof.

14. A method as claimed in claim 10 wherein the step of depositing at least a source/drain metal layer includes depositing a layer of transparent metal oxide on the exposed semiconducting metal oxide prior to depositing the source/drain metal layer.

15. A method as claimed in claim 14 wherein the step of depositing at least the source/drain metal layer includes depositing a barrier metal layer on the layer of transparent metal oxide prior to depositing the source/drain metal layer.

16. A method as claimed in claim 15 wherein the step of depositing the barrier metal layer includes depositing one of Mo, W, Cr, and Ni.

23. A method as claimed in claim 10 wherein the substrate is one of flexible and rigid.

17. A thin film transistor and in-plane-switch LCD electrodes constructed for incorporation into an AMLCD comprising:

a substrate with a surface;

gate metal patterned on the surface of the substrate defining a thin film transistor gate;

a layer of gate dielectric positioned over the gate and surrounding substrate surface;

a layer of semiconducting metal oxide positioned on the layer of gate dielectric;

a channel protection layer on the semiconducting metal oxide overlying the gate, the channel protection layer being patterned to define a channel area in the semiconducting metal oxide above the gate and to expose the remaining semiconducting metal oxide;

at least a source/drain metal layer on the channel protection layer and a portion of the exposed semiconducting metal oxide defining an in-plane-switch area spaced laterally from the channel area and the source/drain metal layer;

the source/drain metal layer being separated into thin film transistor source and drain terminals;

an organic dielectric material positioned on the thin film transistor source and drain terminals and at an opposed side of the in-plane-switch area;

the semiconducting metal oxide defining a first electrode for an in-plane-switch in the in-plane-switch area;

a passivation layer positioned on the organic dielectric material and the first electrode for the in-plane-switch; and

a layer of transparent electrically conductive material positioned on the passivation layer defining a second electrode for the in-plane-switch overlying the first electrode.

18. A thin film transistor and in-plane-switch as claimed in claim 17 wherein the second electrode for the in-plane-switch includes multiple interconnected, spaced apart fingers.

19. A thin film transistor and in-plane-switch as claimed in claim 17 wherein the layer of semiconducting metal oxide includes an amorphous metal oxide.

20. A thin film transistor and in-plane-switch as claimed in claim 17 wherein the at least a source/drain metal layer includes a transparent metal oxide positioned on the layer of semiconducting metal oxide and a barrier metal layer positioned on the layer of transparent metal oxide with the source/drain metal layer positioned on the barrier metal layer.

21. A thin film transistor and in-plane-switch as claimed in claim 17 wherein the organic dielectric material defines bonding pads and the layer of transparent electrically conductive material is positioned over at least part of the bonding pads to provide access for external electrical connections.

24. A thin film transistor and in-plane-switch as claimed in claim 17 wherein the substrate is one of flexible and rigid.

25. A thin film transistor and in-plane-switch as claimed in claim 17 including a backpanel circuit for LPS AMLCD displays with TFT and IPS LCD electrodes.