PERFORMANCE ENHANCEMENT IN TRANSISTORS BY REDUCING THE RECESSING OF ACTIVE REGIONS AND REMOVING SPACERS

• US 20120235215A1
• Filed: 03/15/2012
• Published: 09/20/2012
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Flachowsky, Stefan, Hoentschel, Jan
• Granted Patent: US 8,822,298 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a protective liner above an active region and a gate electrode structure formed on said active region, said gate electrode comprising a dielectric cap layer;

forming drain and source extension regions in said active region in the presence of said protective liner;

forming a spacer structure on said protective liner;

removing an exposed portion of said protective liner by using said spacer structure as an etch mask; and

forming drain and source regions by forming deep drain and source areas in said active region in the presence of said spacer structure.

2. The method of claim 1, further comprising removing said spacer structure by using a non-removed portion of said protective liner as an etch stop material.

3. The method of claim 2, further comprising removing said dielectric cap layer, wherein said dielectric cap layer and said spacer structure are removed in the same etch process.

4. The method of claim 3, further comprising forming a metal silicide in said gate electrode structure and said drain and source regions.

5. The method of claim 1, further comprising forming a strain-inducing dielectric material above said drain and source regions and above said gate electrode structure.

6. The method of claim 1, further comprising performing an implantation process so as to introduce a counter doping species in the presence of said protective liner.

7. The method of claim 1, wherein forming said spacer structure comprises depositing a silicon oxide material and patterning said silicon oxide material so as to form a spacer element.

8. The method of claim 7, further comprising forming said dielectric cap layer from a silicon oxide material.

9. The method of claim 1, further comprising forming said gate electrode structure with a gate length of 40 nm or less.

10. A method, comprising:

forming a protective liner above an active region of a transistor, said protective liner covering a gate electrode structure formed on said active region;

forming drain and source extension regions by incorporating a drain and source dopant species in said active region through said protective liner;

forming a spacer element on sidewalls of said gate electrode structure;

forming drain and source regions in said active region by using said spacer element as an implantation mask; and

removing said spacer element and a dielectric cap layer of said gate electrode structure after forming said drain and source regions.

11. The method of claim 10, wherein said spacer element and said dielectric cap layer are removed by performing a common etch process.

12. The method of claim 11, wherein performing said common etch process further comprises preparing exposed surface areas of said drain and source regions for forming a metal silicide therein.

13. The method of claim 10, wherein forming said spacer element comprises depositing a silicon oxide material on said protective liner and patterning said silicon oxide material by using said protective liner as an etch stop layer.

14. The method of claim 10, further comprising forming said gate electrode structure so as to include a high-k dielectric material.

15. The method of claim 10, further comprising patterning said protective liner by using said spacer element as an etch mask.

16. The method of claim 15, wherein said protective liner is patterned prior to forming said drain and source regions.

17. The method of claim 15, wherein said protective liner is patterned after forming said drain and source regions.

18. The method of claim 10, further comprising forming a strain-inducing dielectric layer above said active region and said gate electrode structure after removing said spacer element.

19. A semiconductor device, comprising:

an active region formed above a substrate;

a gate electrode structure formed on said active region, said gate electrode structure comprising an electrode material and a gate dielectric layer including a high-k dielectric material;

a protective liner having a first portion formed on sidewalls of said electrode material and said gate dielectric layer, said protective liner having a second portion formed on said active region;

drain and source regions formed in said active region; and

a strain-inducing dielectric material formed adjacent to and in contact with said protective liner.

20. The semiconductor device of claim 19, further comprising a metal silicide formed in said drain and source regions, wherein a lateral offset of said metal silicide from said electrode material is substantially determined by said second portion of said protective liner.