INTER-POLY DIELECTRIC IN A SHIELDED GATE MOSFET DEVICE

• US 20120235229A1
• Filed: 03/16/2011
• Published: 09/20/2012
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean E.
• Granted Patent: US 8,610,205 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric.

Claims

1. An apparatus, comprising:

a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric and aligned along the axis;

a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis, the plane intersecting the shield electrode;

a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode; and

a gate dielectric having a portion disposed on the first inter-poly dielectric.

2. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the portion of the first inter-poly dielectric is disposed between a second portion of the second inter-poly dielectric intersecting the plane and the first portion of the second inter-poly dielectric.

3. The apparatus of claim 1, wherein the portion of the first inter-poly dielectric and the portion of the second inter-poly dielectric are disposed lateral to the axis and are disposed above the shield dielectric.

4. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the second inter-poly dielectric has a second portion disposed between the portion of the first inter-poly dielectric and the shield dielectric.

5. The apparatus of claim 1, wherein the portion of the second inter-poly dielectric is a first portion, and the second inter-poly dielectric has a second portion disposed between the shield electrode and the portion of the gate dielectric.

6. The apparatus of claim 1, wherein the first inter-poly dielectric is a different type of dielectric than the second inter-poly dielectric.

7. The apparatus of claim 1, wherein the first inter-poly dielectric is a deposited oxide, and the second inter-poly dielectric is a thermally grown oxide.

8. The apparatus of claim 1, wherein the gate dielectric is a thermally grown oxide, and the shield dielectric is at least one of a thermally grown oxide or a deposited oxide.

9. An apparatus, comprising:

a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric and aligned along the axis;

a first inter-poly dielectric having a portion defining a ring aligned along a plane intersecting the shield electrode, the plane being orthogonal to the axis;

a second inter-poly dielectric having a portion disposed between the portion of the first inter-poly dielectric and the shield electrode; and

a gate dielectric having a portion coupled to the first inter-poly dielectric.

10. The apparatus of claim 9, wherein the portion of the second inter-poly dielectric is a first portion of the second inter-poly dielectric, the second inter-poly dielectric has a second portion aligned along the plane and disposed between the portion of the first inter-poly dielectric and a wall defined by the trench.

11. The apparatus of claim 9, wherein the portion of the gate dielectric is coupled to the second inter-poly dielectric.

12. The apparatus of claim 9, wherein the portion of the second inter-poly dielectric defines a ring aligned along the plane.

13. The apparatus of claim 9, wherein the trench defines a wall that has a first location intersecting a line orthogonal to the axis and a second location intersecting the line, and the gate dielectric has a portion that extends along the line from the first location to the second location.

14. The apparatus of claim 9, wherein the first inter-poly dielectric is formed within the trench after the second inter-poly dielectric is formed within the trench.

15. An apparatus, comprising:

a shield dielectric disposed within a trench within an epitaxial layer of a semiconductor;

a shield electrode disposed within the shield dielectric;

an inter-poly dielectric having a first portion coupled to the shield dielectric and a second portion coupled to the shield electrode, the inter-poly dielectric having a top surface defining a concave shape; and

a gate dielectric having a portion disposed on the top surface of the inter-poly dielectric.

16. The apparatus of claim 15, wherein the inter-poly dielectric is a first deposited oxide, the gate dielectric is a first thermally grown oxide, and the shield dielectric is at least one of a second thermally grown oxide or a second deposited oxide.

17. The apparatus of claim 15, wherein the top surface of the inter-poly dielectric, the shield electrode, and the gate dielectric are aligned along a longitudinal axis,

the first portion of the inter-poly dielectric is disposed adjacent to a wall of the shield electrode.

18. The apparatus of claim 15, wherein the inter-poly dielectric, when deposited, has a thickness that is less than a thickness of the shield dielectric disposed the shield electrode.

19. The apparatus of claim 15, wherein the portion of the gate dielectric is a first portion of the gate dielectric, the gate dielectric has a second portion coupled to at least a portion of the shield dielectric, and the first portion of the gate dielectric is disposed adjacent to the second portion of the gate dielectric.

20. A method, comprising:

forming a shield electrode within a shield dielectric disposed within a trench of an epitaxial layer of a semiconductor;

removing a first portion of the shield dielectric disposed above the shield electrode so that a second portion of the shield dielectric remains coupled to a wall of the trench; and

forming, within the trench, an inter-poly dielectric having a thickness along the second portion of the shield dielectric less than a combined thickness of the first portion of the shield dielectric and the second portion of the shield dielectric.

21. The method of claim 20, wherein the removing includes removing the first portion of the shield dielectric to form a recess adjacent to a wall of the shield electrode before the forming the inter-poly dielectric, the forming the inter-poly dielectric including forming the inter-poly dielectric within the recess.

22. The method of claim 20, further comprising:

exposing a portion of the wall of the trench by removing a portion of the inter-poly dielectric and at least a portion of the second portion of the shield electrode.