FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING

• US 20120235247A1
• Filed: 03/17/2011
• Published: 09/20/2012
• Est. Priority Date: 03/17/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cai, Ming, Guo, Dechao, Yeh, Chun-chen, Lin, Chung-hsun
• Granted Patent: US 8,513,131 B2
• Time in Patent Office: Days
• US Class Current: 257/392
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Claims

1. A method of forming an integrated circuit (IC), the method comprising:

forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and

etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

2. The method of claim 1, wherein the thickness of the first plurality FINFET channel regions corresponds to a first threshold voltage that is different from a second threshold voltage corresponding to the thickness of the second plurality of FINFET channel regions.

3. The method of claim 2, wherein the first threshold voltage and the second threshold voltage range from about 150 millivolts to about 300 millivolts.

4. The method of claim 1, wherein the thickness of the first plurality of spacers and the thickness of the second plurality of spacers range from about 1 nanometer to about 12 nanometers.

5. The method of claim 1, wherein forming the first and second plurality of spacers on a substrate comprises:

forming a plurality of mandrels on the substrate;

depositing a spacer material over the mandrels;

depositing a hardmask over the spacer material;

removing a first portion of the hardmask from a first area of the spacer material corresponding to the first plurality of spacers;

etching the spacer material from which the first portion of the hardmask was removed for a first etch time to form the first plurality of spacers;

removing a second portion of the hardmask from a second area of the spacer material corresponding to the second plurality of spacers;

etching the spacer material from which the second portion of the hardmask was removed for a second etch time to form the second plurality of spacers.

6. The method of claim 5, wherein the mandrels are formed by etching a top layer of the substrate.

7. The method of claim 5, wherein the mandrels comprise one of polysilicon and amorphous silicon.

8. The method of claim 5, wherein the spacer material comprises nitride.

9. The method of claim 5, wherein the hardmask comprises one of high density plasma (HDP) oxide or high-aspect-ratio process (HARP) oxide.

10. The method of claim 5, wherein etching the spacer material comprises a directional reactive ion etch.

11. The method of claim 5, wherein the first etch time is different from the second etch time, and wherein the first etch time determines the thickness of the first plurality of spacers, and wherein the second etch time determines the thickness of the second plurality of spacers.

12. The method of claim 5, further comprising covering the first plurality of spacers with a protective layer during the etch of the second plurality of spacers, and removing the protective layer after the etch of the second plurality of spacers.

13. The method of claim 12, wherein the protective layer comprises one of an oxide and photoresist.

14. The method of claim 5, further comprising:

removing a third portion of the hardmask from a third area of the spacer material corresponding to a third plurality of spacers having a third thickness;

etching the spacer material from which the third portion of the hardmask was removed for a third etch time to form the third plurality of spacers.

15. The method of claim 1, wherein the substrate further comprises an oxide layer located over the silicon layer, and wherein the oxide layer is etched during the etching of the silicon layer.

16. An integrated circuit (IC) comprising:

a first plurality of fin field effect transistors (FINFETs) and a second plurality of FINFETs located on a substrate, the first plurality of FINFETs having a first channel thickness corresponding to a first threshold voltage, and the second plurality of FINFETs having a second channel thickness corresponding to a second threshold voltage, wherein the first channel thickness is different from the second channel thickness, and the first threshold voltage is different from the second threshold voltage.

17. The IC of claim 16, wherein the first threshold voltage and the second threshold voltage range from about 150 millivolts to about 300 millivolts.

18. The IC of claim 16, wherein the thickness of the first plurality of spacers and the thickness of the second plurality of spacers range from about 1 nanometer to about 12 nanometers.

19. The IC of claim 16, further comprising a third plurality of FINFETs having a third channel thickness corresponding to a third threshold voltage, the third channel thickness and the third threshold voltage being different from the first and second channel thicknesses and the first and second threshold voltages.