ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE

• US 20120235716A1
• Filed: 05/31/2012
• Published: 09/20/2012
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: Franck Dahan, Gilles Dubost, Hugh Thomas Mair, Sylvain Dubois
• Original Assignee: Franck Dahan, Gilles Dubost, Hugh Thomas Mair, Sylvain Dubois
• Inventors: Dahan, Franck, Mair, Hugh Thomas, Dubois, Sylvain, DUBOST, GILLES
• Granted Patent: US 8,278,980 B1
• Time in Patent Office: Days
• US Class Current: 327/147
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/22 using more than one loop

Abstract

An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

Claims

1-11. -11. (canceled)

12. A method for a digital phase lock loop high speed bypass mode, the method comprising:

providing a first digital phase lock loop in a first clock domain having a high speed clock;

providing at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input;

controlling the first output of the first glitchless multiplexer according to preselected settings using a device power manager synchronized locally to ensure proper switching; and

controlling a second output of the second glitchless multiplexer using a control logic element of the at least one second digital phase lock loop, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

13. The method of claim 12, wherein the first digital phase lock loop supplies the high speed clock to the at least one second digital phase lock loop.

14. The method of claim 12, wherein controlling the first output of the first glitchless multiplexer according to preselected settings using the device power manager synchronized locally further comprises using a synchronization element disposed in the at least one second digital phase lock loop.

15. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

16. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.

17. The method of claim 12, wherein the low speed system reference clock is input to the core of the at least one second digital phase lock loop.

18. The method of claim 12, wherein the control logic element of the at least one second digital phase lock loop is coupled to the core of the at least one second digital phase lock loop.

19. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

20. The method of claim 12, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.

21-24. -24. (canceled)

25. An apparatus, comprising:

a first digital phase lock loop in a first clock domain having a high speed clock;

at least one second digital phase lock loop in a second clock domain, the at least one second digital phase lock loop having a first glitchless multiplexer having the high speed clock as one input and a low speed system reference clock as another input and a second glitchless multiplexer having a first output of the first glitchless multiplexer as a first input and a synthesized clock from a core of the at least one second digital phase lock loop as a second input;

a device power manager synchronized locally for controlling the first output of the first glitchless multiplexer according to preselected settings; and

a control logic element in the at least one second digital phase lock loop for controlling a second output of the second glitchless multiplexer using, the second output of the second glitchless multiplexer comprising the synthesized clock when the at least one second digital phase lock loop is in a lock mode and comprising the first output of the first glitchless multiplexer when the at least second digital phase lock loop is in the digital phase lock loop high speed bypass mode.

26. The apparatus of claim 25, wherein the first digital phase lock loop supplies the high speed clock to the at least one second digital phase lock loop.

27. The apparatus of claim 25, wherein controlling the first output of the first glitchless multiplexer according to preselected settings using the device power manager synchronized locally further comprises using a synchronization element disposed in the at least one second digital phase lock loop.

28. The apparatus of claim 25, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

29. The apparatus of claim 25, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.

30. The apparatus of claim 25, wherein the low speed system reference clock is input to the core of the at least one second digital phase lock loop.

31. The apparatus of claim 25, wherein the control logic element of the at least one second digital phase lock loop is coupled to the core of the at least one second digital phase lock loop.

32. The apparatus of claim 25, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the high speed clock.

33. The apparatus of claim 25, wherein the first output of the first glitchless multiplexer when the at least one second digital phase lock loop is in the digital phase lock loop high speed bypass mode comprises the low speed system reference clock.