CHARGE PUMP BASED POWER AMPLIFIER ENVELOPE POWER SUPPLY AND BIAS POWER SUPPLY

• US 20120235736A1
• Filed: 09/07/2011
• Published: 09/20/2012
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Levesque, Chris, Southcombe, William David, Jones, David E., Yoder, Scott, Stockert, Terry J.
• Granted Patent: US 8,542,061 B2
• Time in Patent Office: Days
• US Class Current: 330/127
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2200/171 A filter circuit coupled to the output of an amplifier
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/414 A switch being coupled in the output circuit of an amplifier to switch the output on/off
• CPC Class Codes: H03F 2200/417 A switch coupled in the output circuit of an amplifier being controlled by a circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/504 the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21157 A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/602 : Combinations of several amplifiers
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

The present disclosure relates to a direct current (DC)-DC converter, which includes a charge pump based radio frequency (RF) power amplifier (PA) envelope power supply and a charge pump based PA bias power supply. The DC-DC converter is coupled between RF PA circuitry and a DC power supply, such as a battery. As such, the PA envelope power supply provides an envelope power supply signal to the RF PA circuitry and the PA bias power supply provides a bias power supply signal to the RF PA circuitry. Both the PA envelope power supply and the PA bias power supply receive power via a DC power supply signal from the DC power supply. The PA envelope power supply includes a charge pump buck converter and the PA bias power supply includes a charge pump.

Claims

1. Circuitry comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry.

2. The circuitry of claim 1 wherein:

the charge pump buck converter is coupled between the between the RF PA circuitry and a DC power supply; and

the charge pump is coupled between the RF PA circuitry and the DC power supply.

3. The circuitry of claim 2 further comprising the DC power supply.

4. The circuitry of claim 2 wherein the DC power supply is a battery.

5. The circuitry of claim 1 wherein the PA envelope power supply further comprises:

a first inductive element coupled between the charge pump buck converter and first power filtering circuitry; and

the first power filtering circuitry coupled between the first inductive element and the RF PA circuitry.

6. The circuitry of claim 5 wherein the PA bias power supply further comprises second power filtering circuitry coupled between the RF PA circuitry and ground.

7. The circuitry of claim 5 wherein the PA envelope power supply further comprises a buck converter coupled across the charge pump buck converter.

8. The circuitry of claim 5 wherein:

the PA envelope power supply further comprises a buck converter and a second inductive element coupled in series to form a first series coupling; and

the charge pump buck converter and the first inductive element are coupled in series to form a second series coupling, which is coupled across the first series coupling.

9. The circuitry of claim 1 wherein:

the RF PA circuitry comprises a first RF PA having a first final stage and adapted to;

receive an envelope power supply signal;

receive and amplify a first RF input signal to provide a first RF output signal, such that the envelope power supply signal provides power for amplification; and

receive a first final bias signal to bias the first final stage;

the RF PA circuitry further comprises PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal;

the PA bias power supply is adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on DC-DC conversion of the DC power supply signal; and

the PA envelope power supply is adapted to receive the DC power supply signal and provide the envelope power supply signal based on DC-DC conversion of the DC power supply signal.

10. The circuitry of claim 9 wherein:

the PA envelope power supply further comprises a buck converter;

the circuitry further comprises control circuitry adapted to select one of a first converter operating mode and a second converter operating mode;

during the first converter operating mode, the charge pump buck converter is adapted to be active, and the buck converter is adapted to be inactive; and

during the second converter operating mode, the charge pump buck converter is adapted to be inactive, and the buck converter is adapted to be active.

11. The circuitry of claim 9 wherein:

the charge pump buck converter is adapted to receive and convert the DC power supply signal to provide a first buck output signal, such that the envelope power supply signal is based on the first buck output signal; and

the charge pump is adapted to receive and charge pump the DC power supply signal to provide the bias power supply signal.

12. The circuitry of claim 11 further comprising control circuitry adapted to:

select one of a pump buck pump-up operating mode and at least one other pump buck operating mode of the charge pump buck converter, such that during the pump buck pump-up operating mode, a voltage of the envelope power supply signal is greater than a voltage of the DC power supply signal; and

select one of a bias supply pump-up operating mode and at least one other bias supply operating mode of the charge pump, such that during the bias supply pump-up operating mode, a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

13. The circuitry of claim 9 wherein:

the RF PA circuitry comprises a second RF PA having a second final stage and adapted to;

receive the envelope power supply signal;

receive and amplify a second RF input signal to provide a second RF output signal, such that the envelope power supply signal provides power for amplification; and

receive a second final bias signal to bias the second final stage; and

the PA bias circuitry is further adapted to provide the second final bias signal based on the bias power supply signal.

14. The circuitry of claim 13 further comprising control circuitry adapted to select one of a plurality of communications modes comprising a first PA operating mode and a second PA operating mode, such that:

during the first PA operating mode, the first RF PA is further adapted to receive and amplify the first RF input signal to provide the first RF output signal, and the second RF PA is further adapted to be disabled; and

during the second PA operating mode, the second RF PA is further adapted to receive and amplify the second RF input signal to provide the second RF output signal, and the first RF PA is further adapted to be disabled.

15. The circuitry of claim 14 wherein the first RF input signal is a highband RF input signal and the second RF input signal is a lowband RF input signal.

16. The circuitry of claim 14 wherein the control circuitry is further adapted to:

during the first PA operating mode, select a desired magnitude of the first final bias signal and provide a bias configuration control signal to the PA bias circuitry based on the desired magnitude of the first final bias signal, such that the bias configuration control signal is a digital signal; and

during the second PA operating mode, select a desired magnitude of the second final bias signal and provide the bias configuration control signal to the PA bias circuitry based on the desired magnitude of the second final bias signal.

17. The circuitry of claim 16 wherein the PA bias circuitry comprises final stage current digital-to-analog converter (IDAC) circuitry adapted to receive and use the bias power supply signal and the bias configuration control signal in a digital-to-analog conversion to provide:

during the first PA operating mode, the first final bias signal, such that a magnitude of the first final bias signal is about equal to the desired magnitude of the first final bias signal; and

during the second PA operating mode, the second final bias signal, such that a magnitude of the second final bias signal is about equal to the desired magnitude of the second final bias signal.

18. The circuitry of claim 17 wherein the final stage IDAC circuitry further comprises a final stage multiplexer adapted to:

receive the bias configuration control signal;

during the first PA operating mode, receive and forward a final stage bias signal to provide the first final bias signal based on the bias configuration control signal; and

during the second PA operating mode, receive and forward the final stage bias signal to provide the second final bias signal based on the bias configuration control signal, such that the final stage IDAC is further adapted to receive and use the bias power supply signal and the bias configuration control signal in the digital-to-analog conversion to provide the final stage bias signal.

19. The circuitry of claim 18 wherein the final stage multiplexer is further adapted to:

during the first PA operating mode, provide the second final bias signal, which is about zero volts, such that the second RF PA is disabled via the second final bias signal; and

during the second PA operating mode, provide the first final bias signal, which is about zero volts, such that the first RF PA is disabled via the first final bias signal.

20. The circuitry of claim 13 wherein:

the first RF PA is a first multi-mode multi-band quadrature RF PA comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

the second RF PA is a second multi-mode multi-band quadrature RF PA comprising a second quadrature PA path coupled to the antenna port.

21. The circuitry of claim 20 wherein the first quadrature PA path has only one in-phase PA stage and only one quadrature-phase PA stage.

22. The circuitry of claim 13 wherein:

The first RF PA is a first multi-mode multi-band quadrature RF PA coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

The RF PA circuitry further comprises the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

23. The circuitry of claim 1 further comprising:

PA control circuitry coupled between the RF PA circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least a first look-up table (LUT), which is associated with at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus, such that the RF PA circuitry has at least a first RF input and a plurality of RF outputs, wherein;

configuration of the RF PA circuitry associates one of at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with at least the first LUT.

24. A method comprising:

providing a first radio frequency (RF) power amplifier (PA) having a first final stage;

providing PA bias circuitry;

providing a PA envelope power supply having a charge pump buck converter;

providing a PA bias power supply having a charge pump;

receiving an envelope power supply signal;

receiving and amplifying a first RF input signal to provide a first RF output signal, such that the envelope power supply signal provides power for amplification;

receiving a first final bias signal to bias the first final stage;

receiving a bias power supply signal;

providing the first final bias signal based on the bias power supply signal;

receiving a direct current (DC) power supply signal;

providing the bias power supply signal based on DC-DC conversion of the DC power supply signal using the charge pump; and

providing the envelope power supply signal based on DC-DC conversion of the DC power supply signal using the charge pump buck converter.