NON-VOLATILE MEMORY CELL

• US 20120236646A1
• Filed: 05/29/2012
• Published: 09/20/2012
• Est. Priority Date: 06/17/2010
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Ching, Wen-Hao, Hsu, Te-Hsun, Chen, Wei-Ren, Chang, Wen-Chuan
• Granted Patent: US 8,958,245 B2
• Time in Patent Office: Days
• US Class Current: 365/185.14
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

Claims

1. A non-volatile memory cell comprising:

a coupling device formed in a first conductivity region; and

a first select transistor serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region;

wherein an electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate;

wherein the first conductivity region and the second conductivity region are formed in a third conductivity region;

wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.

2. The non-volatile memory cell of claim 1, wherein the first conductivity region and the second conductivity region are a first conductivity type, and the third conductivity region is a second conductivity type.

3. The non-volatile memory cell of claim 1, wherein the floating gate comprises:

a first gate part for forming the coupling device; and

a second gate part for forming the first floating gate transistor;

wherein the first gate part has a gate area larger than the second gate part.

4. The non-volatile memory cell of claim 1, wherein the coupling device is formed by a metal-oxide-semiconductor capacitor or a metal-oxide-semiconductor field effect transistor.

5. The non-volatile memory cell of claim 1, wherein the first floating gate transistor is located between the first select transistor and the second select transistor.

6. The non-volatile memory cell of claim 1, further comprising:

a control line electrically connected to the coupling device;

a word line electrically connected to a gate of the first select transistor;

a select gate electrically connected to a gate of the second select transistor;

a bit line electrically connected to a drain region of the second select gate transistor; and

a source line electrically connected to a source region of the first select transistor.

7. The non-volatile memory cell of claim 6, wherein during a read operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for sensing current conducted through the serially-connected first select transistor, first floating gate transistor and second select transistor.

8. The non-volatile memory cell of claim 7, wherein:

the control-line voltage is in a range from 0V to 5V;

the word-line voltage is in a range from 1V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the bit-line voltage is in a range from 1V to 5V;

the source-line voltage is 0V;

the first well voltage is 0V; and

the second well voltage is in a range from 0V to 5V.

9. The non-volatile memory cell of claim 6, wherein during a program operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing Fowler-Nordheim tunneling injection at the first floating gate transistor.

10. The non-volatile memory cell of claim 9, wherein:

the control-line voltage is in a range from 5V to 20V;

the word-line voltage is in a range from 0V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the bit-line voltage is 0V;

the source-line voltage is 0V;

the first well voltage is 0V; and

the second well voltage is in a range from 5V to 20V.

11. The non-volatile memory cell of claim 6, wherein during a program inhibit operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing voltage boosting of the channel at the first floating gate transistor.

12. The non-volatile memory cell of claim 11, wherein:

the control-line voltage is in a range from 5V to 20V;

the word-line voltage is in a range from 0V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the bit-line voltage is in a range from 1V to 5V;

the source-line voltage is in a range from 0V to 5V;

the first well voltage is 0V; and

the second well voltage is in a range from 5V to 20V.

13. The non-volatile memory cell of claim 6, wherein during an erase operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing Fowler-Nordheim tunneling ejection at the first floating gate transistor.

14. The non-volatile memory cell of claim 13, wherein:

the control-line voltage is 0V;

the word-line voltage is in a range from 5V to 20V;

the select-gate voltage is in a range from 5V to 20V;

the bit-line voltage is in a range from 5V to 20V;

the source-line voltage is in a range from 5V to 20V;

the first well voltage is in a range from 5V to 20V; and

the second well voltage is in a range from 5V to 20V.

15. The non-volatile memory cell of claim 1, further comprising:

a second floating gate transistor formed in a fourth conductivity region, wherein the fourth conductivity region is formed in the third conductivity region, and a gate of the second floating gate transistor, the electrode of the coupling device, and the gate of the first floating gate transistor are the monolithically formed floating gate.

16. The non-volatile memory cell of claim 15, wherein the first conductivity region, the second conductivity region and the fourth conductivity region are a first conductivity type, and the third conductivity region is a second conductivity type.

17. The non-volatile memory cell of claim 15, wherein the floating gate comprises:

a first gate part for forming the coupling device; and

a second gate part for forming the first floating gate transistor and the second floating gate transistor;

wherein the first gate part has a gate area larger than the second gate part.

18. The non-volatile memory cell of claim 15, wherein the coupling device is formed by a metal-oxide-semiconductor capacitor or a metal-oxide-semiconductor field effect transistor.

19. The non-volatile memory cell of claim 15, wherein the second floating gate transistor is formed by a metal-oxide-semiconductor field effect transistor or a metal-oxide-semiconductor capacitor.

20. The non-volatile memory cell of claim 15, wherein the second conductivity region is located between the first conductivity region and the fourth conductivity region.

21. The non-volatile memory cell of claim 15, wherein the fourth conductivity region is located between the first conductivity region and the second conductivity region.

22. The non-volatile memory cell of claim 15, wherein the first floating gate transistor is located between the first select transistor and the second select transistor.

23. The non-volatile memory cell of claim 22, further comprising:

a control line electrically connected to the coupling device;

a word line electrically connected to the gate of the first select transistor;

a select gate electrically connected to the gate of the second select transistor;

an erase line electrically connected to diffusion regions of the second floating gate transistor and the fourth conductivity region;

a bit line electrically connected to a drain region of the second select gate transistor; and

a source line electrically connected to a source region of the first select transistor.

24. The non-volatile memory cell of claim 23, wherein during a read operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for sensing current conducted through the serially-connected first select transistor, first floating gate transistor and second select transistor.

25. The non-volatile memory cell of claim 24, wherein:

the control-line voltage is in a range from 0V to 5V;

the word-line voltage is in a range from 1V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the erase-line voltage is in a range from 0V to 5V;

the bit-line voltage is in a range from 1V to 5V;

the source-line voltage is 0V;

the first well voltage is 0V; and

the second well voltage is in a range from 0V to 5V.

26. The non-volatile memory cell of claim 23, wherein during a program operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing Fowler-Nordheim tunneling injection at the first floating gate transistor.

27. The non-volatile memory cell of claim 26, wherein:

the control-line voltage is in a range from 5V to 20V;

the word-line voltage is in a range from 0V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the erase-line voltage is in a range from 5V to 20V;

the bit-line voltage is 0V;

the source-line voltage is 0V;

the first well voltage is 0V; and

the second well voltage is in a range from 5V to 20V.

28. The non-volatile memory cell of claim 23, wherein during a program inhibit operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing voltage boosting of the channel at the first floating gate transistor.

29. The non-volatile memory cell of claim 28, wherein:

the control-line voltage is in a range from 5V to 20V;

the word-line voltage is in a range from 0V to 5V;

the select-gate voltage is in a range from 1V to 5V;

the erase-line voltage is in a range from 5V to 20V;

the bit-line voltage is in a range from 1V to 5V;

the source-line voltage is in a range from 0V to 5V;

the first well voltage is 0V; and

the second well voltage is in a range from 5V to 20V.

30. The non-volatile memory cell of claim 23, wherein during an erase operation, a control line voltage applied to the control line, a word line voltage applied to the word line, a select gate voltage applied to the select gate, an erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductivity region, and a second well voltage applied to the third conductivity region are configured for inducing Fowler-Nordheim tunneling ejection at the second floating gate transistor.

31. The non-volatile memory cell of claim 30, wherein:

the control-line voltage is 0V;

the word-line voltage is in a range from 0V to 5V;

the select-gate voltage is in a range from 0V to 5V;

the erase-line voltage is in a range from 5V to 20V;

the bit-line voltage is 0V;

the source-line voltage is 0V;

the first well voltage is 0V; and

the second well voltage is in a range from 5V to 20V.