TWO-STAGE BLOCK SYNCHRONIZATION AND SCRAMBLING

• US 20120237032A1
• Filed: 05/31/2012
• Published: 09/20/2012
• Est. Priority Date: 11/03/2004
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ungerboeck, Gottfried, Shen, Ba-Zhong, Powell, Scott Richard
• Application Number:
  US13/485,749
• Publication Number:
  US 20120237032A1
• Time in Patent Office: Days
• US Class Current: 380/268
• CPC Class Codes: H04L 25/03866 using scrambling

Abstract

A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization

PRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.

Claims

1. A method for execution by a receive module, comprising:

receiving, by the receive module, a frame via a transmission medium, the frame including a synchronization bit and a scrambled payload;

producing state bits from the synchronization bit and previously received synchronization bits in previously received frames by the receive module;

producing N stream descrambling bits based on the state bits for the frame by the receive module; and

combining the N stream descrambling bits with the scrambled payload of the frame to obtain N payload bits.

2. The method of claim 1, wherein the combining the N stream descrambling bits with the scrambled payload of the frame comprises:

modulo-2 adding the N stream descrambling bits with the scrambled payload of the frame to obtain the N payload bits.

3. The method of claim 1, wherein:

the producing the state bits for the frame is performed via a recover-synchronization Pseudo Random Number Generation process; and

the producing the N stream descrambling bits is performed via a descramble Pseudo Random Number Generation process that is initialized with the state bits and clocked N times per frame.

4. The method of claim 3, wherein the recover-synchronization Pseudo Random Number Generation process comprises:

performing a continuously operating Maximum-Length Shift Register (MLSR) function with primitive-polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2<sup>m−

1</sup>-1 zeros, wherein the state bits include m preceding output bits, and, within one period, m-tuple of the state bits cycles through 2^m-1 non-zero binary m-tuples.

5. The method of claim 3, wherein the descramble Pseudo Random Number Generation process comprises:

performing a continuously operating Maximum-Length Shift Register (MLSR) function with primitive-polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2<sup>m−

1</sup>-1 zeros, wherein m state bits include m preceding output bits, and, within one period, m-tuple of them state bits cycles through 2^m-1 non-zero binary m-tuples.

6. The method of claim 3, further comprising:

initializing the descramble Pseudo Random Number Generation process at a starting point of subsequence of the N scrambling bits within a 2^m2-1-periodic sequence in accordance with a continuous operation, where, for given primitive polynomials, transfer of the state bits from the recover-synchronization Pseudo Random Number Generation process to the descramble Pseudo Random Number Generation process occurs in a manner such that the subsequences of the N descrambling bits start at pseudo-randomly distributed starting points, which include the starting point.

7. The method of claim 6, further comprising:

reversing order of the state bits transferred from the recover-synchronization Pseudo Random Number Generation process to the descramble Pseudo Random Number Generation process when the given primitive polynomials includes two primitive polynomials that are identical with degree m;

generating a 2^m-1-periodic sequence by the recover-synchronization Pseudo Random Number Generation process; and

producing, by the descramble Pseudo Random Number Generation process, the subsequences of length N starting at pseudo-randomly distributed points within the 2^m-1-periodic sequence, wherein the state bits produced via the recover-synchronization Pseudo Random Number Generation process cycle through 2^m-1 non-zero binary m-tuples and length-N subsequences includes 2^m-1 starting points.

8. The method of claim 6, further comprising:

maintaining order of transferring the state bits from the recover-synchronization Pseudo Random Number Generation process to the descramble Pseudo Random Number Generation process when the given primitive polynomials includes two primitive polynomials of same degree m with time-reversed coefficients relative to each of the two primitive polynomials.

9. The method of claim 1, further comprising:

utilizing a fly-wheel technique to recover the state bits reliably in the presence of transmission errors.

10. A receive module, comprising:

a synchronization and descramble module coupled to receive a frame including a synchronization bit and a scrambled payload, produce state bits from the synchronization bit and previously received synchronization bits from previously received frames, produce N stream descrambling bits based on the state bits for the frame by the receive module and combine the N stream descrambling bits with the scrambled payload of the frame to obtain N payload bits; and

a frame recovery module coupled to receive the N payload bits and recover the frame using the N payload bits.

11. The receive module of claim 10, wherein the synchronization and descramble module comprises:

a modulo-2 adder coupled to add the N stream descrambling bits with the scrambled payload of the frame.

12. The receive module of claim 10, wherein the synchronization and descramble module comprises:

a recover-synchronization Pseudo Random Number Generator (PRNG) for generating the state bits for the frame from the synchronization bit and the previously received synchronization bits; and

a descramble Pseudo Random Number Generator (PRNG), the descramble PRNG being initialized with the state bits and clocked N times per frame to generate the N stream descrambling bits.

13. The receive module of claim 12, wherein the recover-synchronization Pseudo Random Number Generator further comprises:

a continuously operating Maximum-Length Shift Register (MLSR) with primitive-polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2m<sup>−

1</sup>-1 zeros, wherein the state bits include m preceding output bits, and, within one period, m-tuple of the state bits cycles through 2^m-1 non-zero binary m-tuples.

14. The receive module of claim 12, wherein the descramble Pseudo Random Number Generator further comprises:

a continuously operating Maximum-Length Shift Register (MLSR) with primitive-polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2<sup>m−

1</sup>-1 zeros, wherein m state bits include m preceding output bits, and, within one period, m-tuple of the m state bits cycles through 2^m-1 non-zero binary m-tuples.

15. The receive module of claim 12, wherein the descramble Pseudo Random Number Generator further functions to:

initialize at a starting point of subsequence of the N descrambling bits within a 2^m2-1-periodic sequence in accordance with a continuous operation, where, for given primitive polynomials, transfer of the state bits from the recover-synchronization Pseudo Random Number Generator to the descramble Pseudo Random Number Generator occurs in a manner such that the subsequences of the N descrambling bits start at pseudo-randomly distributed starting points, which including the starting point.

16. The receive module of claim 12, wherein the recover-synchronization Pseudo Random Number Generator further functions to:

reverse order of the state bits transferred to the descramble Pseudo Random Number Generator when the given primitive polynomials includes two primitive polynomials that are identical with degree m;

generate a 2^m-1-periodic sequence; and

produce the subsequences of length N starting at pseudo-randomly distributed points within the 2^m-1-periodic sequence, wherein the state bits cycle through 2^m-1 non-zero binary m-tuples and length-N subsequences includes 2^m-1 starting points.

17. The receive module of claim 12, wherein the recover-synchronization Pseudo Random Number Generator further functions to:

maintain order of transferring the state bits to the descramble Pseudo Random Number Generator when the given primitive polynomials includes two primitive polynomials of same degree m with time-reversed coefficients relative to each of the two primitive polynomials.

18. A synchronization and descrambling module comprises:

a frame storage module for receiving a currently received frame via a transmission medium, the currently received frame including a synchronization bit and a scrambled payload;

a recover-synchronization pseudo random number generator (PRNG) module for receiving the synchronization bit from the currently received frame and previously received synchronization bits from previously received frames and producing state bits from the synchronization bit and the previously received synchronization bits;

a descramble PRNG module clocked N times per PCS frame to produce a cipher stream based on the state bits; and

a summing module operably coupled to sum the cipher stream and the scrambled payload of the currently received frame to obtain a PCS frame payload.

19. The synchronization and descrambling module of claim 18, wherein the recover-synchronization PRNG comprises:

a continuously operating Maximum-Length Shift Register (MLSR) with primitive-polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2<sup>m−

1</sup>-1 zeros, wherein the state bits include m preceding output bits, and, within one period, m-tuple of the state bits cycles through 2^m-1 non-zero binary m-tuples.

20. The synchronization and descrambling module of claim 18, wherein the descramble PRNG comprises:

a continuously operating Maximum-Length Shift Register (MLSR) with primitive polynomial feedback of degree m to produce a pseudo random binary sequence with period length 2^m-1 that includes 2<sup>m−

1</sup> ones and 2<sup>m−

1</sup>-1 zeros, wherein m state bits include m preceding output bits, and, within one period, m-tuple of the m state bits cycles through 2^m-1 non-zero binary m-tuples.