MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20120238056A1
• Filed: 02/08/2012
• Published: 09/20/2012
• Est. Priority Date: 03/15/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NUMAZAKI, Masato
• Granted Patent: US 8,828,805 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/78301 Capillary
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85051 Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips.

Claims

1. A manufacturing method of a semiconductor device comprising the steps of:

(a) providing a lead frame including a die pad comprised of a quadrangle having a pair of first sides opposed to each other and a pair of second sides intersecting with the first sides and opposed to each other, a first lead group arranged along one of the two first sides of the die pad in the plan view, a second lead group arranged along the other of the two first sides of the die pad in the plan view, and a plurality of suspending leads connecting to the second sides of the die pad, respectively;

(b) mounting a first semiconductor chip having a first front surface, a plurality of first bonding pads formed on the first front surface, and a first back surface opposite to the first front surface, in a first area of the die pad, and mounting a second semiconductor chip having a second front surface, a plurality of second bonding pads formed on the second front surface, and a second back surface opposite to the second front surface, in a second area of the die pad positioned next to the first area in the plan view;

(c) electrically connecting a plurality of external bonding pads of the first bonding pads and a plurality of external bonding pads of the second bonding pads with the first lead group and the second lead group via a plurality of external wires, respectively, and electrically connecting a plurality of internal bonding pads of the first bonding pads with a plurality of internal bonding pads of the second bonding pads via a plurality of internal wires; and

(d) supplying resin from one side to the other side of the second sides of the die pad, and sealing the die pad, the first semiconductor chip, the second semiconductor chip, the external wires and the internal wires with the resin,

wherein the second area is positioned between the first area and the other of the second sides of the die pad in the plan view,

wherein the internal bonding pads of the first semiconductor chip include a first pad group and a second pad group,

wherein the internal bonding pads of the second semiconductor chip include a third pad group and a fourth pad group,

wherein the internal wires include a plurality of first internal wires electrically connecting the first pad group and the third pad group, respectively, and a plurality of second internal wires electrically connecting the second pad group and the fourth pad group, respectively,

wherein a distance between the first pad group and the second pad group is larger than a distance between the third pad group and the fourth pad group, and

wherein the distance between the first pad group and the second pad group is larger than the length of some of the internal bonding pads.

2. The manufacturing method of the semiconductor device according to claim 1,

wherein a distance between the first semiconductor chip and the second semiconductor chip is smaller than or equal to the width of one lead in the first lead group or the second lead group.

3. The manufacturing method of the semiconductor device according to claim 1,

wherein the first pad group is electrically connected with a digital internal interface circuit of the first semiconductor chip and the second pad group is electrically connected with an analog internal interface circuit of the first semiconductor chip,

wherein the third pad group is electrically connected with a digital internal interface circuit of the second semiconductor chip and the fourth pad group is electrically connected with an analog internal interface circuit of the second semiconductor chip,

wherein the first internal wires are a plurality of internal digital wires respectively electrically connecting the first pad group with the third pad group, and

wherein the second internal wires are a plurality of internal analog wires respectively electrically connecting the second pad group with the fourth pad group.

4. The manufacturing method of the semiconductor device according to claim 1,

wherein at the step (b), the first area and the second area are discriminated by recognizing cutout portions formed in the first sides of the die pad.

5. The manufacturing method of the semiconductor device according to claim 1,

wherein at the step (b), the first area and the second area are discriminated by recognizing an oddly-shaped lead different in shape in the plan view from the other leads of a plurality of leads in either or both of the first lead group and the second lead group.

6. The manufacturing method of the semiconductor device according to claim 1,

wherein at the step (c), the first semiconductor chip side is taken as a first bond for wire bonding and the second semiconductor chip side is taken as a second bond for wire bonding.

7. The manufacturing method of the semiconductor device according to claim 6,

wherein at the second bond, wire bonding is carried out on a bump electrode formed over the second semiconductor chip.

8. The manufacturing method of the semiconductor device according to claim 1,

wherein the pitch of the bonding pads of the first semiconductor chip is narrower than the pitch of the bonding pads of the second semiconductor chip.

9. The manufacturing method of the semiconductor device according to claim 1,

wherein the pitch of the bonding pads of the second semiconductor chip is narrower than the pitch of the bonding pads of the first semiconductor chip, and

where at the step (c), the second semiconductor chip side is taken as a first bond for wire bonding and the first semiconductor chip side is taken as a second bond for wire bonding.

10. The manufacturing method of the semiconductor device according to claim 1,

wherein the chip size of the first semiconductor chip is smaller than the chip size of the second semiconductor chip in the plan view.

11. The manufacturing method of the semiconductor device according to claim 1,

wherein the arrangement of the first bonding pads of the first semiconductor chip is a three-side pad arrangement in which the first bonding pads are arranged along three sides of the first front surface of the first semiconductor chip, and

wherein a lead is not arranged in a position corresponding to the second sides of the die pad.

12. The manufacturing method of the semiconductor device according to claim 1,

wherein the inner portion of each of a plurality of leads comprising the first lead group and the second lead group is bent from the outer portion of each of the leads toward the die pad in the plan view.

13. The manufacturing method of the semiconductor device according to claim 1,

wherein in the first semiconductor chip, another circuit is arranged between a digital interface circuit and an analog interface circuit, and

wherein in the second semiconductor chip, the other circuit is arranged between a digital interface circuit and an analog interface circuit.

14. The manufacturing method of the semiconductor device according to claim 1,

wherein part of the first lead group and part of the second lead group are protruded form side surfaces of a sealing body formed by the step (d).

15. The manufacturing method of the semiconductor device according to claim 1,

wherein part of the first lead group and part of the second lead group are exposed from the lower surface of a sealing body formed by the step (d).

16. The manufacturing method of the semiconductor device according to claim 1,

wherein the thickness of the first semiconductor chip is larger than the thickness of the second semiconductor chip.

17. The manufacturing method of the semiconductor device according to claim 1

wherein at the step (d), the resin is passed through the area between the first pad group and the second pad group of the first semiconductor chip and filled in the area between the first semiconductor chip and the second semiconductor chip.

18. A manufacturing method of a semiconductor device comprising the steps of:

(a) providing a lead frame including a die pad comprised of a quadrangle having a pair of first sides opposed to each other and a pair of second sides intersecting with the first sides and opposed to each other, a first lead group arranged along one of the two first sides of the die pad in the plan view, a second lead group arranged along the other of the two first sides of the die pad in the plan view, and a plurality of suspending leads connecting to the second sides of the die pad, respectively;

(b) mounting a first semiconductor chip having a first front surface, a plurality of first bonding pads formed on the first front surface, and a first back surface located on the opposite side to the first front surface in a first area of the die pad, and mounting a second semiconductor chip having a second front surface, a plurality of second bonding pads formed on the second front surface, and a second back surface opposite to the second front surface, in a second area of the die pad positioned next to the first area in the plan view;

(c) electrically connecting a plurality of external bonding pads of the first bonding pads and a plurality of external bonding pads of the second bonding pads with the first lead group and the second lead group via a plurality of external wires, respectively and electrically connecting a plurality of internal bonding pads of the first bonding pads with a plurality of internal bonding pads of the second bonding pads via a plurality of internal wires; and

(d) supplying resin from one side to the other side of the second sides of the die pad, and sealing the die pad, the first semiconductor chip, the second semiconductor chip, the external wires, and the internal wires with the resin,

wherein the second area is positioned between the first area and the other of the two second sides of the die pad in the plan view, and

wherein the thickness of the first semiconductor chip is larger than the thickness of the second semiconductor chip.