Methods of Fabricating Semiconductor Devices

• US 20120238093A1
• Filed: 03/13/2012
• Published: 09/20/2012
• Est. Priority Date: 03/15/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sang-yong, Lee, Woon-kyung, Park, Jin-taek
• Granted Patent: US 8,906,805 B2
• Time in Patent Office: Days
• US Class Current: 438/675
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method of fabricating a semiconductor device includes forming a stacked structure in which 2ⁿ (here, n is an integer which is 2 or more) deposited sacrificial layers and 2ⁿ deposited insulating layers disposed on the 2ⁿ deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2ⁿ−1 first recesses penetrating 2⁰ through 2ⁿ⁻¹ deposited sacrificial layers and forming a buried insulating layer group including 2ⁿ−1 buried insulating layers filling the 2ⁿ−1 first recesses respectively. A contact plug group including 2ⁿ contact plugs penetrating an uppermost deposited insulating layer of the 2ⁿ deposited insulating layers and the 2ⁿ−1 buried insulating layers may be formed.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a stacked structure of alternatingly deposited sacrificial layers and insulating layers on an upper surface of a substrate, the upper surface extending in a first direction and a second direction that is substantially perpendicular to the first direction, the stacked structure extending in a third direction that is substantially perpendicular to the first direction and the second direction;

forming a recess group that includes a plurality of first recesses that penetrate the sacrificial layers except a first one of the deposited sacrificial layer;

forming a buried insulating layer group that includes buried insulating layers that are configured to substantially fill the plurality of first recesses;

forming a contact plug group that includes contact plugs that are configured to penetrate an uppermost one of the insulating layers and the buried insulating layers;

wherein forming the stacked structure includes forming 2ⁿ deposited sacrificial layers and 2ⁿ deposited insulating layers, wherein n is an integer that is greater than or equal to two, and wherein forming the recess group is performed by n quantity etch processes, each of the etch processes removing a portion of the stacked structure.

2. The method according to claim 1, wherein the plurality of first recesses are disposed in the first direction.

3. The method according to claim 1, wherein ones of the plurality of first recesses are formed in a hole shape.

4. The method according to claim 1, wherein ones of the plurality of first recesses are formed in a linear shape that extends in the second direction.

5. The method according to claim 1, wherein at least two adjacent ones of the first recesses are united.

6. The method according to claim 1, wherein an m-th etch process of the n etch processes is performed so that, in the stacked structure, a cross sectional area of a portion removed by the m-th etch process is larger than that removed by an m−

1-th etch process of the n etch processes, and

wherein m is an integer in a range from 2 to n.

7. The method according to claim 1, wherein the substrate includes 2ⁿ contact formation regions,

wherein ones of the contact plugs are formed in different ones of the contact formation regions, and

wherein forming the first recess group includes forming ones of the plurality of the first recesses in 2ⁿ−

1 ones of the contact formation regions of the stacked structure.

8. The method according to claim 7, wherein the n etch processes are performed to penetrate 2^k deposited sacrificial layers, respectively, and

wherein k is an integer in a range from 0 through n−

1.

9. The method according to claim 8, wherein one of the n etch processes performed to penetrate the 2^k deposited sacrificial layers is simultaneously performed in all of 2^k successively adjacent contact formation regions.

10. The method according to claim 1, further comprising:

after forming the buried insulating layer group,

removing the 2ⁿ deposited sacrificial layers; and

filling first conductive material in a portion of spaces in which the 2ⁿ deposited sacrificial layers are removed.

11. The method according to claim 10, wherein removing the 2ⁿ deposited sacrificial layers comprises:

dividing the stacked structure into a plurality of divided stacked structures extending in the first direction;

removing portions of the 2ⁿ deposited sacrificial layers included in the plurality of divided stacked structures; and

filling the first conductive material in the spaces in which the 2ⁿ deposited sacrificial layers are removed, and

wherein forming the contact plug group comprises forming a plurality of contact plug groups corresponding to the plurality of divided stacked structures, respectively.

12. The method according to claim 1, further comprising:

after forming the buried insulating layer group, forming a sacrificial plug group including 2ⁿ sacrificial plugs contacting the deposited sacrificial layers, respectively, by penetrating an uppermost deposited insulating layer of the deposited insulating layers and the buried insulating layers, respectively; and

removing the sacrificial plug group and the deposited sacrificial layers,

wherein forming the contact plug group comprises filling conductive material in a portion of spaces in which the deposited sacrificial layers are removed and in a space in which the sacrificial plug group is removed.

13. The method according to claim 1, wherein the stacked structure is formed on a memory cell region in which non-volatile memory cells are formed, a contact plug region in which the contact plugs are formed, and a stack dividing region, and the n etch processes remove portions of the stack dividing region so as to penetrate 2⁰ through 2ⁿ⁻

1 deposited sacrificial layers, respectively, centering around a same location of the stack dividing region,

further comprising, after forming the recess group, forming a second recess so as to penetrate an lowest deposited sacrificial layer, centering around the same location of the stack dividing region.

14. A method of fabricating a semiconductor device, the method comprising:

forming a stacked structure in which 2ⁿ first material layers and 2ⁿ second material layers are stacked on a substrate, each of the first material layers and each of the second material layers being alternately deposited on each other; and

forming 2ⁿ−

1 recesses penetrating a quantity of from 2⁰ to 2ⁿ−

1 of the first material layers, respectively, so as that the 2ⁿ−

1 recesses expose the quantity of 2ⁿ−

1 of the first material layers from the substrate at bottoms of the recesses, respectively,

wherein the 2ⁿ−

1 recesses are formed by a combination of etch processes for penetrating 2^k first material layers, and

wherein n is an integer that is greater than or equal to two and k is an integer in a range from 0 to n−

1.

15. The method according to claim 14, wherein etch processes performed to penetrate a same number of the first material layers from among etch processes for forming the 2ⁿ−

1 recesses are simultaneously performed.

16. The method according to claim 14, wherein portions of the stacked structure in which 2ⁿ⁻

1 recesses of the 2ⁿ−

1 recesses are to be formed are respectively removed in etch processes for forming the 2ⁿ−

1 recesses.

17. A method of fabricating a semiconductor device, the method comprising:

forming a stacked structure in which 2ⁿ (here, n is an integer which is 2 or more) deposited sacrificial layers and 2ⁿ deposited insulating layers disposed on the 2ⁿ deposited sacrificial layers respectively are alternately deposited in a third direction that is perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other;

forming a recess group including 2ⁿ−

1 first recesses penetrating 2ⁿ through 2ⁿ−

1 deposited sacrificial layers, respectively, from an uppermost deposited sacrificial layer of the 2ⁿ deposited sacrificial layers;

forming a buried insulating layer group including 2ⁿ−

1 buried insulating layers filling the 2ⁿ−

1 first recesses respectively; and

forming a contact plug group including 2ⁿ contact plugs penetrating an uppermost deposited insulating layer of the 2ⁿ deposited insulating layers and the 2ⁿ−

1 buried insulating layers, respectively,

wherein n is an integer that is at least 2, and

wherein forming the recess group is performed by n etch processes to remove a portion of the stacked structure.

18. The method according to claim 17, further comprising:

after forming the buried insulating layer group,

removing the 2ⁿ deposited sacrificial layers; and

filling first conductive material in a portion of spaces in which the 2ⁿ deposited sacrificial layers are removed.

19. The method according to claim 18, wherein removing the 2ⁿ deposited sacrificial layers comprises:

dividing the stacked structure into a plurality of divided stacked structures extending in the first direction;

removing portions of the 2ⁿ deposited sacrificial layers included in the plurality of divided stacked structures; and

filling the first conductive material in the spaces in which the 2ⁿ deposited sacrificial layers are removed, and

wherein forming the contact plug group comprises forming a plurality of contact plug groups corresponding to the plurality of divided stacked structures, respectively.

20. The method according to claim 17, further comprising:

after forming the buried insulating layer group, forming a sacrificial plug group including 2ⁿ sacrificial plugs contacting the 2ⁿ deposited sacrificial layers, respectively, by penetrating the uppermost deposited insulating layer of the 2ⁿ deposited insulating layers and the 2ⁿ−

1 buried insulating layers, respectively; and

removing the sacrificial plug group and the 2ⁿ deposited sacrificial layers,

wherein forming the contact plug group comprises filling conductive material in a portion of spaces in which the 2ⁿ deposited sacrificial layers are removed and in a space in which the sacrificial plug group is removed.