DEVICE PERFORMANCE PARMETER TUNING METHOD AND SYSTEM

• US 20120239178A1
• Filed: 03/15/2011
• Published: 09/20/2012
• Est. Priority Date: 03/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chun-Hsien, Mou, Jong-I, Wu, Sunny, Chen, Kun-Ming, Hsieh, Dung-Yian, Lin, Hui-Ru, Wang, Jo Fei, Chu, I-Ching
• Granted Patent: US 8,452,439 B2
• Time in Patent Office: Days
• US Class Current: 700/104
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.

Claims

1. A method comprising:

(a) computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests, each regression model outputting a wafer yield measure as a function of a plurality of device performance variables;

(b) for each failure bin, determining sensitivity of the wafer yield measure to each of the plurality of device performance variables, and ranking the device performance variables with respect to sensitivity of the wafer yield measure;

(c) selecting a subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other;

(d) combining the wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables, to provide a combined wafer yield measure;

(e) selecting at least one new process parameter value to effect a change in the one device performance variable, based on the combined wafer yield measure, the at least one new process parameter value to be used to process at least one additional wafer.

2. The method of claim 1, wherein step (a) includes normalizing the wafer yield measures and values of the device performance variables to a common dimensionless scale.

3. The method of claim 1, wherein the sensitivity of the wafer yield measure to one of the plurality of device performance variables is determined by a partial derivative of the wafer yield measure with respect to that device performance variable, evaluated at an average value of that device performance variable in its respective failure bin.

4. The method of claim 1, wherein step (c) includes:

selecting up to a first predetermined number of device parameter variables having the highest sensitivities for a given failure bin; and

de-selecting any of the selected device parameter variables for which a correlation coefficient with respect to a more highly ranked one of the device parameter variables is greater than a threshold value.

5. The method of claim 1, wherein step (d) includes summing the wafer yield measures for each failure bin.

6. The method of claim 5, wherein step (d) further includes adding to the sum of wafer yield measures a component based on a Mahalanobis distance between a given device parameter value and a current device target for that same device parameter.

7. The method of claim 6, wherein the component is computed by multiplying the Mahanobis distance by a weighting coefficient.

8. The method of claim 7, wherein step (e) includes determining a minimum value of the combined wafer yield measure within a tunable range of the device parameter value.

9. The method of claim 8, wherein the range is limited to two standard deviations from a device parameter value used in the wafer electrical tests.

10. The method of claim 1, wherein the combined wafer yield measure gives a preference to new process parameter values that are close to a current value of the same process parameter.

11. The method of claim 1, wherein step (e) includes:

selecting a new value of the one device performance variable, and

identifying a process parameter value corresponding to the new value of the one device performance variable to be the at least one new process parameter value.

12. The method of claim 11, wherein:

the step of identifying the process parameter includes performing a table lookup in a table identifying a change in the process parameter that will cause a given change in the one device performance variable; and

the table is based on data previously collected from a test wafer during a design of experiment specific to a process technology of the wafer.

13. The method of claim 1, further comprising, before step (a):

performing the wafer electrical tests on a plurality of semiconductor wafers and identifying the respective failures of some of the wafers to satisfy a plurality of performance objectives in the wafer electrical tests; and

assigning the identified failures to respective ones of the failure bins according to which performance objective was not met by a given one of the wafers.