APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION

• US 20120239858A1
• Filed: 07/06/2011
• Published: 09/20/2012
• Est. Priority Date: 07/07/2010
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MELIK-MARTIROSIAN, Ashot
• Granted Patent: US 8,737,141 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.

Claims

1. A method for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:

storing a parameter, the operating condition being a function of the parameter;

monitoring a memory operation for a trigger event; and

on the trigger event, adjusting the parameter in accordance with a circuit characteristic associated with the memory block, and

providing to the memory circuit a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the parameter to adjust the operating condition.

2. The method of claim 1, wherein each pulse in the series of pulses is an incremental step pulse such that an amplitude of each pulse is incrementally increased with each increasing pulse number, starting from a start magnitude.

3. The method of claim 1, wherein the trigger event includes a number of program/erase (P/E) cycles.

4. The method of claim 3, wherein adjusting the parameter in accordance with the circuit characteristic includes indexing a lookup table by the number of P/E cycles to determine the parameter.

5. The method of claim 3, wherein the number of P/E cycles is a range of P/E cycles, a current P/E cycle being in the range of P/E cycles.

6. The method of claim 1, wherein the operating condition includes a voltage distribution and adjusting the operating condition includes reducing a width of an upper portion of the voltage distribution and increasing a programming time, and adjusting the parameter in accordance with a circuit characteristic includes reducing the parameter.

7. The method of claim 6, wherein the trigger event includes the programming time reaching a minimum programming duration.

8. The method of claim 1, wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of a lower portion of the voltage distribution and reducing a programming time, and adjusting the parameter in accordance with a circuit characteristic includes increasing the parameter.

9. The method of claim 1, wherein the parameter is a start magnitude.

10. The method of claim 1, wherein the parameter is a step magnitude.

11. The method of claim 1, wherein the parameter is a pulse width.

12. The method of claim 1, wherein the operating condition includes an erase time, and adjusting the operating condition includes reducing the erase time, and adjusting the parameter in accordance with a circuit characteristic includes increasing the parameter.

13. The method of claim 12, wherein the trigger event includes the erase time reaching a minimum erase duration.

14. A control circuit for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:

a memory interface configured to be operably coupled to the memory circuit; and

a controller, wherein the controller is configured to;

store a parameter, the operating condition being a function of the parameter,

monitor a memory operation for a trigger event, and,

on the trigger event, adjust the parameter in accordance with a circuit characteristic associated with the memory block, and

provide to the memory interface a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the parameter to adjust the operating condition.

15. The control circuit of claim 14, wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of an upper portion of the voltage distribution and increasing a programming time, wherein the controller being configured to adjust the parameter in accordance with the circuit characteristic includes the controller being configured to reduce the parameter.

16. The control circuit of claim 14, wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of a lower portion of the voltage distribution and reducing a programming time, wherein the controller being configured to adjust the parameter in accordance with a circuit characteristic includes the controller being configured to increase the parameter.

17. The control circuit of claim 14, wherein the operating condition includes an erase time, and adjusting the operating condition includes reducing the erase time, wherein the controller being configured to adjust the parameter in accordance with a circuit characteristic includes the controller being configured to increase the parameter.

18. The control circuit of claim 14, wherein the trigger event is a range of P/E cycles, and wherein the controller being configured to monitor the memory operation for the trigger event includes the controller being configured to determine that a current number of P/E cycles is within the range of P/E cycles.

19. A system for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:

a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;

a memory interface operably coupled to the memory circuit;

a storage medium interface operably coupled to a volatile memory; and

a controller operably coupled to the host interface, wherein the controller is operable to;

store a parameter in the volatile memory, the operating condition being a function of the parameter,

monitor a memory operation for a trigger event, and,

on the trigger event, adjust the parameter in accordance with a circuit characteristic associated with the memory block, and

provide to the memory circuit a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the parameter to adjust the operating condition.

20. The system of claim 19, wherein the operating condition is a voltage distribution in the memory block, and wherein the memory circuit is configured to, in response to the command, apply the series of voltage pulses to the group of cells in the memory block in accordance with the parameter to adjust a width of the voltage distribution, each pulse in the series of pulses being an incremental step pulse such that an amplitude of each pulse is incrementally increased with each increasing pulse number, starting from a start magnitude.

21. The system of claim 19, wherein the trigger event includes a number of P/E cycles and the circuit characteristic includes an adjustment value associated with the number of P/E cycles, wherein the controller being configured to adjust the parameter in accordance with the circuit characteristic includes the controller being configured to index a lookup table stored on the volatile memory by the number of P/E cycles to determine the adjustment value.

22. A method for populating a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:

identifying a desired condition limit;

computing a first parameter as a function of a first memory operation to be performed on the memory block, the operating condition being a function of the parameter;

including the first parameter in the parameter set;

cycling the memory block until the operating condition reaches the desired condition limit;

determining after the cycling a second parameter as a function of a second memory operation to be performed on the memory block;

including the second parameter in the parameter set;

repeating the cycling and the determining and the including the second parameter steps until a desired number of cycles is reached;

performing a retention bake on the memory circuit;

performing a read operation on the memory block; and

verifying a bit error rate resulting from the read operation does not exceed a desired error rate.

23. The method of claim 22, wherein the first and second memory operations are programming operations, the operating condition is a programming time, and the condition limit is a minimum programming duration.

24. The method of claim 22, wherein the first and second memory operations are programming operations, the operating condition is an erase time, and the condition limit is a maximum erase duration.

25. The method of claim 22, wherein the first and second memory operations are programming operations, the operating condition is a voltage threshold distribution in the memory block, and the condition limit is a maximum distribution width.