Flash Memory Device and Control Method

• US 20120239868A1
• Filed: 09/23/2010
• Published: 09/20/2012
• Est. Priority Date: 09/23/2009
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: National Digital Research Centre
• Inventors: Ryan, Conor Maurice, Sullivan, Joseph
• Granted Patent: US 8,984,210 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

The present invention is directed to a method for increasing the operational lifetime of a flash memory device, wherein, the method comprises varying the operating parameters of the flash memory device over the lifetime of the flash memory device. The advantage of providing a method which varies the operating parameters of a flash memory device is that the operational lifetime of the flash memory device will be increased. Relatively low voltages and relatively short voltage periods may be used initially to write to, read from and erase the flash cells in the flash memory device. As time passes, the flash cells in the flash memory device will begin to degrade and it will be necessary to increase the voltage and the period of the voltage applied to the flash memory device in order to ensure that the correct write, read and/or erase commands are carried out. The invention is also directed towards a flash memory device.

Claims

1. A method for increasing the operational efficiency of a flash memory device, wherein, the method comprises the step of adjusting one or more operating parameters of the flash memory device over the lifetime of the flash memory device;

characterised in that, the method comprises the steps of tracking an operating age of the flash memory device, and adjusting the one or more operating parameters of the flash memory device as a pre-calibrated function of the tracked operating age of the flash memory device.

2. A method for increasing the operational efficiency of a flash memory device as claimed in claim 1, wherein, one or more values held in a control register, which values determines one or more operating parameters of the flash memory device, are adjusted over the lifetime of the flash memory device;

and the values held in the control register are adjusted on multiple occasions over the lifetime of the flash memory device.

6. A method for increasing the operational efficiency of a flash memory device as claimed in claim 1, wherein, the method further comprises a step of calibrating the flash memory device during a manufacturing stage by selecting an optimum set of operating parameters for the flash memory device from a plurality of different sets of operating parameters based on testing the flash memory device.

7. A method for increasing the operational efficiency of a flash memory device as claimed in claim 6, wherein, the testing in the step of calibrating the flash memory device during the manufacturing stage is carried out on one or more pre-specified bad blocks within the flash memory device.

9. A method for increasing the operational efficiency of a flash memory device as claimed in claim 1, wherein, the method further comprises the step of analysing the type of operations performed by the flash memory device over a preset time period, and adjusting the one or more operating parameters of the flash memory device in response to the analysis.

10. A method for increasing the operational efficiency of a flash memory device as claimed in claim 1, wherein, the method is carried out by placing the flash memory device into a test mode in order to calibrate, adjust and/or adapt the one or more operating parameters of the flash memory device.

12. A method for increasing the operational efficiency of a flash memory device as claimed in claim 1, wherein, the method further comprises modifying the one or more operating parameters in order to adjust one or more thresholds of a logic level in the flash memory device over the lifetime of the flash memory device.

3. (canceled)

4. (canceled)

5. (canceled)

8. (canceled)

11. (canceled)

13. A flash memory device comprising an array of memory blocks and a controller, wherein, the controller is used to manage write and erase operations on the array of memory blocks;

whereby, the controller comprises an operating parameters management unit which is used to vary one or more operating parameters of the memory blocks in the flash memory device over the lifetime of the flash memory device;

characterized in that, the controller is operable to track an operating age of the flash memory device and to adjust the one or more operating parameters of the flash memory device as a pre-calibrated function of the tracked operating age of the memory device.

14. A flash memory device as claimed in claim 13, wherein one or more values held in a control register, which values determines one or more operating parameters of the flash memory device, are adjusted over the lifetime of the flash memory device;

and the one or more values held in the control register are adjusted on multiple occasions over the lifetime of the flash memory device.

15. A flash memory device as claimed in claim 13, wherein, the one or more operating parameters of the flash memory device are adjusted on multiple occasions over the lifetime of the flash memory device.

17. A flash memory device as claimed in claim 14, wherein, the one or more values held in the control register are increased over the lifetime of the flash memory device.

18. A flash memory device as claimed in claim 13, wherein, the flash memory device is calibrated during manufacture by selecting an optimum set of operating parameters for the flash memory device from a plurality of different sets of operating parameters based on testing the flash memory device.

19. A flash memory device as claimed in claim 18, wherein, the testing of the flash memory device is carried out on one or more pre-specified bad blocks within the flash memory device.

21. A flash memory device as claimed in claim 13, wherein, the controller analyses the type of operations performed by the flash memory device over a preset time period, and adjusts the one or more operating parameters of the flash memory device in response to the analysis.

22. A flash memory device as claimed in claim 13, wherein, the flash memory device is placed into a test mode in order to calibrate, adjust and/or adapt the one or more operating parameters of the flash memory device.

23. A flash memory device as claimed in claim 13, wherein, a specific batch of flash memory devices are analysed to ascertain one or more operating parameters that are ideally suited to that particular batch of flash memory devices.

24. A flash memory device as claimed in claim 13, wherein, the controller modifies the one or more operating parameters in order to adjust one or more thresholds of a logic level in the flash memory device over the lifetime of the flash memory device.

25. A flash memory device as claimed in claim 13, wherein the one or more operating parameters comprises one or more of a program current, a program voltage, an erase current, an erase voltage, a number of repeat cycles and a rate of repeat cycles for a performing a programme and/or erase operation, a threshold voltage, a threshold current and a pass threshold.

26. A flash memory device as claimed in claim 13, wherein a first communications link is established between the array of memory blocks and the controller for managing write and erase operations, and a second separate communications link is established between the array of memory blocks and the controller for varying the one or more operating parameters of the memory blocks in the flash memory device.

16. (canceled)

20. (canceled)

27. A flash memory device comprising an array of memory blocks and a controller, wherein, the controller is used to manage write and erase operations on the array of memory blocks;

whereby, the controller comprises an operating parameters management unit which is used to vary one or more operating parameters of the memory blocks in the flash memory device over the lifetime of the flash memory device;

characterised in that, the controller analyses the type of operations performed by the flash memory device over a preset time period, and adjusts one or more operating parameters of the flash memory device in response to the analysis.