APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION

• US 20120239991A1
• Filed: 03/09/2011
• Published: 09/20/2012
• Est. Priority Date: 07/02/2010
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MELIK-MARTIROSIAN, Ashot
• Granted Patent: US 8,819,503 B2
• Time in Patent Office: Days
• US Class Current: 714/708
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic associated with the memory block. The parameter may be a new read level voltage to apply to a page of a memory block, or a program verify level voltage used to program a page of a memory block. On determining the parameter a command is sent to the memory circuit to apply the parameter to the page of the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.

Claims

1. A method for adjusting a memory parameter associated with a non-volatile memory circuit, comprising:

monitoring the memory circuit for a trigger event; and

on the trigger event;

determining the memory parameter in accordance with a circuit characteristic associated with a memory block of the memory circuit; and

providing to the memory circuit a command representative of an instruction to apply the determined memory parameter to a group of memory cells of the memory block.

2. The method of claim 1, wherein the memory parameter is an adjusted program verify level.

3. The method of claim 2, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the retention time to obtain the adjusted program verify level.

4. The method of claim 3, wherein determining the memory parameter includes the adjusted program verify level being set to a higher value than a current verify level.

5. The method of claim 1, wherein the memory parameter is an adjusted read level.

6. The method of claim 5, wherein the trigger value is a cycle limit and the circuit characteristic is a number of P/E cycles, the trigger event occurring when the number of P/E cycles reaches the cycle limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the number of P/E cycles to obtain the adjusted read level.

7. The method of claim 6, wherein determining the memory parameter includes the adjusted read level being set to a higher value than a current read level.

8. The method of claim 5, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the retention time to obtain the adjusted read level.

9. The method of claim 8, wherein determining the memory parameter includes the adjusted read level being set to a lower value than a current read level.

10. The method of claim 5, wherein the instruction to apply the memory parameter to the group of cells includes a command to read the group of memory cells, the method further comprising:

obtaining a bit error rate in conjunction with reading the group of memory cells;

verifying the bit error rate is an unacceptable value; and

on verifying the bit error rate is the unacceptable value;

estimating a new read level that will produce an acceptable bit error rate;

providing to the memory circuit a command representative of an instruction to apply the new read level to the group of memory cells to re-read the group; and

repeating the steps of obtaining, verifying, estimating and providing until the bit rate is an acceptable value.

11. A machine-readable medium including machine-executable instructions for performing a method for adjusting a memory parameter associated with a non-volatile memory circuit, the method comprising the steps of:

monitoring the memory circuit for a trigger event; and

on the trigger event;

determining the memory parameter in accordance with a circuit characteristic associated with a memory block of the memory circuit; and

providing to the memory circuit a command representative of an instruction to apply the determined memory parameter to a group of memory cells of the memory block.

12. The machine-readable medium of claim 11, wherein the memory parameter is an adjusted program verify level.

13. The machine-readable medium of claim 12, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the retention time to obtain the adjusted program verify level.

14. The machine-readable medium of claim 13, wherein determining the memory parameter includes the adjusted program verify level being set to a higher value than a current verify level.

15. The machine-readable medium of claim 11, wherein the memory parameter is an adjusted read level.

16. The machine-readable medium of claim 15, wherein the trigger value is a cycle limit and the circuit characteristic is a number of P/E cycles, the trigger event occurring when the number of P/E cycles reaches the cycle limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the number of P/E cycles to obtain the adjusted read level.

17. The machine-readable medium of claim 16, wherein determining the memory parameter includes the adjusted read level being set to a higher value than a current read level.

18. The machine-readable medium of claim 15, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein determining the memory parameter in accordance with a circuit characteristic includes indexing a lookup table by the retention time to obtain the adjusted read level.

19. The machine-readable medium of claim 18, wherein determining the memory parameter includes the adjusted read level being set to a lower value than a current read level.

20. The machine-readable medium of claim 15, wherein the instruction to apply the memory parameter to the group of cells includes a command to read the group of memory cells, the method further comprising:

obtaining a bit error rate in conjunction with reading the group of memory cells;

verifying the bit error rate is an unacceptable value; and

on verifying the bit error rate is the unacceptable value;

estimating a new read level that will produce an acceptable bit error rate;

providing to the memory circuit a command representative of an instruction to apply the new read level to the group of memory cells to re-read the group; and

repeating the steps of obtaining, verifying, estimating and providing until the bit rate is an acceptable value.

21. A system for adjusting a memory parameter associated with a non-volatile memory circuit, comprising:

a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;

a memory interface operably coupled to the memory circuit;

a storage medium interface operably coupled to a volatile memory; and

a controller operably coupled to the host interface, wherein the controller is operable to;

monitor the memory circuit for a trigger event; and

on the trigger event;

determine the memory parameter in accordance with a circuit characteristic associated with a memory block of the memory circuit; and

provide to the memory circuit a command representative of an instruction to apply the determined memory parameter to a group of memory cells of the memory block.

22. The system of claim 21, wherein the memory parameter is an adjusted program verify level.

23. The system of claim 22, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein the controller being operable to determine the memory parameter in accordance with a circuit characteristic includes the controller being operable to index a lookup table by the retention time to obtain the adjusted program verify level.

24. The system of claim 23, wherein determining the memory parameter includes controller being operable to set the adjusted program verify level to a higher value than a current verify level.

25. The system of claim 21, wherein the memory parameter is an adjusted read level.

26. The system of claim 25, wherein the trigger value is a cycle limit and the circuit characteristic is a number of P/E cycles, the trigger event occurring when the number of P/E cycles reaches the cycle limit, and wherein the controller being operable to determine the memory parameter in accordance with a circuit characteristic includes the controller being operable to index a lookup table by the number of P/E cycles to obtain the adjusted read level.

27. The system of claim 26, wherein the controller being operable to determine the memory parameter includes controller being operable to set the adjusted read level to a higher value than a current read level.

28. The system of claim 25, wherein the trigger value is a retention limit and the circuit characteristic is a retention time, the trigger event occurring when the retention time of the memory block reaches the retention limit, and wherein the controller being operable to determine the memory parameter in accordance with a circuit characteristic includes the controller being operable to index a lookup table by the retention time to obtain the adjusted read level.

29. The system of claim 28, wherein the controller being operable to determine the memory parameter includes the controller being operable to set the adjusted read level to a lower value than a current read level.