APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE

• US 20120240012A1
• Filed: 07/06/2011
• Published: 09/20/2012
• Est. Priority Date: 07/07/2010
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: MELIK-MARTIROSIAN, Ashot, WEATHERS, Anthony D., BARNDT, Richard D.
• Granted Patent: US 8,656,256 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/03 Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words

Abstract

Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.

Claims

1. A method for operating a multi-level cell (MLC) flash memory circuit, the method comprising the steps of:

reading data from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode;

performing error correction on the read data to correct read errors in the read data;

determining if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switching the operating mode of the memory block from the MLC mode to the SLC mode.

2. The method of claim 1, further comprising:

erasing the memory block;

writing data to the memory block in SLC mode;

reading the data from the memory block;

performing error correction on the read data to correct read errors in the read data;

determining if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switching the operating mode of the memory block from the SLC mode to the defective mode.

3. The method of claim 1, the switching comprising:

selecting an available memory block from the plurality of memory blocks;

moving the data from the memory block to the available memory block;

marking the memory block as invalid; and

assigning the operating mode of the memory block to the SLC mode.

4. The method of claim 3, wherein the data is associated with an address mapped to the memory block before the data is moved to the available memory block, and wherein moving the data from the memory block to the available memory block comprises mapping the address associated with the data to the available memory block.

5. The method of claim 1, wherein the memory block operating in the MLC mode is configured to store four states per cell, and wherein the memory block operating in the SLC mode is configured to store two states per cell.

6. The method of claim 5, wherein the memory block comprises a plurality of pages, including a most significant bit (MSB) page and a least significant bit (LSB) page.

7. The method of claim 6, wherein the switching the operating mode of the memory block from the MLC mode to the SLC mode comprises instructing the MLC flash memory circuit to use the LSB page and not the MSB page.

8. A system for adjusting a memory parameter associated with a multi-level cell (MLC) flash memory circuit, comprising:

a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;

a memory interface operably coupled to the MLC flash memory circuit;

a storage medium interface operably coupled to a volatile memory; and

a controller operably coupled to the host interface, wherein the controller is operable to;

read data from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode;

perform error correction on the read data to correct read errors in the read data;

determine if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switch the operating mode of the memory block from the MLC mode to the SLC mode.

9. The system of claim 8, wherein the controller is further operable to:

erase the memory block;

write data to the memory block in SLC mode;

read the data from the memory block;

perform error correction on the read data to correct read errors in the read data;

determine if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switch the operating mode of the memory block from the SLC mode to the defective mode.

10. The system of claim 8, wherein the switching the operating mode comprises:

selecting an available memory block from the plurality of memory blocks;

moving the data from the memory block to the available memory block;

marking the memory block as invalid; and

assigning the operating mode of the memory block to the SLC mode.

11. The system of claim 10, wherein the data is associated with an address mapped to the memory block before the data is moved to the available memory block, and wherein moving the data from the memory block to the available memory block comprises mapping the address associated with the data to the available memory block.

12. The system of claim 8, wherein the memory block operating in the MLC mode is configured to store four states per cell, and wherein the memory block operating in the SLC mode is configured to store two states per cell.

13. The system of claim 12, wherein the memory block comprises a plurality of pages, including a most significant bit (MSB) page and a least significant bit (LSB) page.

14. The system of claim 13, wherein the switching the operating mode of the memory block from the MLC mode to the SLC mode comprises instructing the MLC flash memory circuit to use the LSB page and not the MSB page.

15. A machine-readable medium including machine-executable instructions for performing a method for operating a multi-level cell (MLC) flash memory circuit, the method comprising the steps of:

reading data from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode;

performing error correction on the read data to correct read errors in the read data;

determining if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switching the operating mode of the memory block from the MLC mode to the SLC mode.

16. The machine-readable medium of claim 15, the method further comprising:

erasing the memory block;

writing data to the memory block in SLC mode;

reading the data from the memory block;

performing error correction on the read data to correct read errors in the read data;

determining if a number of bits corrected by the error correction exceeds a predetermined threshold value; and

if the number of bits corrected by the error correction exceeds the predetermined threshold value, switching the operating mode of the memory block from the SLC mode to the defective mode.

17. The machine-readable medium of claim 15, the switching comprising:

selecting an available memory block from the plurality of memory blocks;

moving the data from the memory block to the available memory block;

marking the memory block as invalid; and

assigning the operating mode of the memory block to the SLC mode.

18. The machine-readable medium of claim 17, wherein the data is associated with an address mapped to the memory block before the data is moved to the available memory block, and wherein moving the data from the memory block to the available memory block comprises mapping the address associated with the data to the available memory block.

19. The machine-readable medium of claim 15, wherein the memory block operating in the MLC mode is configured to store four states per cell, and wherein the memory block operating in the SLC mode is configured to store two states per cell.

20. The machine-readable medium of claim 19, wherein the memory block comprises a plurality of pages, including a most significant bit (MSB) page and a least significant bit (LSB) page.