SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20120241856A1
• Filed: 06/01/2012
• Published: 09/27/2012
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Yoshito Nakazawa, Yuji Yatsuda
• Original Assignee: Yoshito Nakazawa, Yuji Yatsuda
• Inventors: NAKAZAWA, Yoshito, YATSUDA, Yuji
• Granted Patent: US 8,604,563 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n⁺-type semiconductor region of the protective diode are formed in the same step.

Claims

1. A semiconductor device comprising:

a drain region of a field-effect transistor formed over a semiconductor substrate;

a channel region of the field-effect transistor formed over the drain region;

a source region of the field-effect transistor formed over the channel region;

a trench reaching the drain region from an upper surface of the source region;

a first insulating film formed in the trench and disposed at a lower part of the trench;

a first gate electrode of the field-effect transistor formed over the first insulating film in the trench and disposed at the lower part of the trench;

a second insulating film formed in the trench and disposed at a upper part of the trench; and

a second gate electrode of the field-effect transistor formed over the second insulating film in the trench and disposed at the upper part of the trench,

wherein a first lead-out part of the first gate electrode is formed in an outer peripheral portion of the trench and is electrically connected with the first gate electrode,

wherein a second lead-out part of the second gate electrode is formed in the outer peripheral portion of the trench and is electrically connected with the second gate electrode,

wherein a thickness of the first lead-out part is smaller than a thickness of the second lead-out part,

wherein the first gate electrode and the first lead-out part include a first conductive film, respectively, and

wherein the second gate electrode and the second lead-out part include a second conductive film, respectively.

2. A semiconductor device according to the claim 1,

wherein a thickness of the first gate electrode formed in the trench is smaller than a thickness of the second gate electrode formed in the trench.

3. A semiconductor device according to the claim 2,

wherein the first gate electrode and the second gate electrode are electrically connected to the same potential.

4. A semiconductor device according to the claim 2,

wherein the first gate electrode and the second gate electrode are electrically connected to a different potential, and

wherein the first gate electrode and the source region are electrically connected to the same potential.

5. A semiconductor device according to the claim 1,

wherein the first conductive film is made of a first poly silicon film, respectively, and

wherein the second conductive film is made of a second poly silicon film, respectively.

6. A semiconductor device according to the claim 5,

wherein an impurity concentration of the first poly silicon film is lower than an impurity concentration of the second poly silicon film.

7. A semiconductor device according to the claim 6,

wherein the first poly silicon film has a n-type conductivity, and

wherein the second poly silicon film has a n-type conductivity.

8. A semiconductor device according to the claim 7,

wherein the drain region has a n-type conductivity,

wherein the channel region has a p-type conductivity, and

wherein the source region has a n-type conductivity.