SEMICONDUCTOR DEVICE

• US 20120241858A1
• Filed: 09/22/2011
• Published: 09/27/2012
• Est. Priority Date: 03/23/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shimizu, Mariko, Komatsu, Kanako, Morioka, Jun, Shirai, Koji, Takahashi, Keita, Yamada, Tsubasa
• Granted Patent: US 8,421,153 B2
• Time in Patent Office: Days
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A first semiconductor layer extends from the element region to the element-termination region, and functions as a drain of the MOS transistor. A second semiconductor layer extends, below the first semiconductor layer, from the element region to the element-termination region. A third semiconductor layer extends from the element region to the element-termination region, and is in contact with the second semiconductor layer to function as a drift layer of the MOS transistor. A distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the fifth semiconductor layer side in the element region is smaller than that between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the fifth semiconductor layer side in the element-termination region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an element region formed on the semiconductor substrate, and including an MOS transistor formed thereon;

an element termination region formed on the semiconductor substrate and formed at an end region of the element region;

a first semiconductor layer of a first conductivity type formed to extend in a first direction as its lengthwise direction from the element region to the element termination region, the first semiconductor layer having a first impurity concentration, the first semiconductor layer functioning as a drain region of the MOS transistor in the element region;

a second semiconductor layer of the first conductivity type formed to extend in the first direction as its lengthwise direction from the element region to the element termination region, the second semiconductor layer being formed in a layer below the first semiconductor layer, the second semiconductor layer having a second impurity concentration that is smaller than the first impurity concentration;

a third semiconductor layer of the first conductivity type formed to extend in the first direction as its lengthwise direction from the element region to the element termination region, the third semiconductor layer having a third impurity concentration that is smaller than the second impurity concentration, the third semiconductor layer being arranged in contact with the second semiconductor layer to function as a drift layer of the MOS transistor;

a field oxide film formed on a surface of the third semiconductor layer and in contact with the first semicondutor layer;

a fourth semiconductor layer of a second conductivity type formed on the semiconductor layer to extend in the first direction as its lengthwise direction from the element region to the element termination region, the fourth semiconductor layer functioning as a channel region of the MOS transistor in the element region;

a fifth semiconductor layer of the first conductivity type formed on a surface of the fourth semiconductor layer and functioning as a source region of the MOS transistor; and

a gate electrode formed on a surface of the semiconductor substrate between the third semiconductor layer and the fourth semiconductor layer, via a gate insulating film,

a distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the side of the fifth semiconductor layer in the element region is smaller than a distance between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the side of the fifth semiconductor layer in the element termination region.

2. The semiconductor device according to claim 1, wherein

the element region and the element termination region are divided into a plurality of rectangular areas, the rectangular areas having the same width along a second direction perpendicular to the first direction,

the first semiconductor layer and the second semiconductor layer are arranged substantially at a center in the second direction of the rectangular areas, and

the fifth semiconductor layer is arranged at an end portion in the second direction of the rectangular areas.

3. The semiconductor device according to claim 2, wherein

a width of the second semiconductor layer along the second direction in the element termination region is larger than a width of the second semiconductor layer along the second direction in the element region.

4. The semiconductor device according to claim 3, wherein

a width of the fourth semiconductor layer along the second direction in the element termination region is smaller than a width of the fourth semiconductor layer along the second direction in the element region.

5. The semiconductor device according to claim 3, wherein

a planar shape of the second semiconductor layer in the vicinity of an end of the first semiconductor is a polygon.

6. The semiconductor device according to claim 1, wherein the first semiconductor layer has a rectangular shape with its lengthwise direction along the first direction.

7. The semiconductor device according to claim 6, wherein

a length of the field oxide film along a second direction perpendicular to the first direction in the element termination region is larger than a length of the field oxide film along the second direction in the element region.

8. The semiconductor device according to claim 2, wherein

a planar shape of the second semiconductor layer in the vicinity of an end of the first semiconductor is a polygon.

9. The semiconductor device according to claim 1, wherein

a width of the second semiconductor layer along a second direction perpendicular to the first direction in the element termination region is larger than a width of the second semiconductor layer along the second direction in the element region.

10. The semiconductor device according to claim 1, wherein

a width of the fourth semiconductor layer along a second direction perpendicular to the first direction in the element termination region is smaller than a width of the fourth semiconductor layer along the second direction in the element region.

11. The semiconductor device according to claim 1, wherein

a planar shape of the second semiconductor layer in the vicinity of an end of the first semiconductor is a polygon.

12. A semiconductor device, comprising:

a semiconductor substrate;

an element region formed on the semiconductor substrate, and including an MOS transistor formed thereon;

an element termination region formed on the semiconductor substrate and formed at an end region of the element region;

a first semiconductor layer of a first conductivity type formed to extend in a first direction as its lengthwise direction from the element region to the element termination region, the first semiconductor layer having a first impurity concentration, the first semiconductor layer functioning as a drain region of the MOS transistor in the element region;

a second semiconductor layer of a first conductivity type formed to extend in the first direction as its lengthwise direction from the element region to the element termination region, the second semiconductor layer being formed in a layer below the first semiconductor layer, the second semiconductor layer having a second impurity concentration that is smaller than the first impurity concentration;

a third semiconductor layer of the first conductivity type formed to extend in the first direction as its lengthwise direction from the element region to the element termination region, the third semiconductor layer having a third impurity concentration that is smaller than the second impurity concentration, the third semiconductor layer being arranged in contact with the second semiconductor layer to function as a drift layer of the MOS transistor;

a fourth semiconductor layer of a second conductivity type formed on the semiconductor layer to extend in the first direction as its lengthwise direction from the element region to the element termination region, the fourth semiconductor layer functioning as a channel region of the MOS transistor in the element region;

a fifth semiconductor layer of the first conductivity type formed on a surface of the fourth semiconductor layer and functioning as a source region of the MOS transistor; and

a gate electrode formed on a surface of the semiconductor substrate between the third semiconductor layer and the fourth semiconductor layer, via a gate insulating film,

regarding a section along a second direction perpendicular to the first direction, a width of the third semiconductor layer in the element termination region is larger than a width of the third semiconductor layer in the element region.

13. The semiconductor device according to claim 12, wherein

the element region and the element termination region are divided into a plurality of rectangular areas, the rectangular areas having the same width along the second direction,

the first semiconductor layer and the second semiconductor layer are arranged substantially at a center in the second direction of the rectangular areas, and

the fifth semiconductor layer is arranged at an end portion in the second direction of the rectangular areas.

14. The semiconductor device according to claim 13, wherein

a width of the second semiconductor layer along the second direction in the element termination region is larger than a width of the second semiconductor layer along the second direction in the element region.

15. The semiconductor device according to claim 14, wherein

a planar shape of the second semiconductor layer in the vicinity of an end of the first semiconductor is a polygon.

16. The semiconductor device according to claim 13, wherein

a width of the fourth semiconductor layer along the second direction in the element termination region is smaller than a width of the fourth semiconductor layer along the second direction in the element region.

17. The semiconductor device according to claim 12, further comprising a field oxide film formed on the surface of the third semiconductor layer.

18. The semiconductor device according to claim 17, wherein

a length of the field oxide film along the second direction in the element termination region is larger than a length of the field oxide film along the second direction in the element region.

19. A semiconductor device, comprising:

a semiconductor substrate;

an element region formed on the semiconductor substrate, and including an MOS transistor formed thereon;

an element termination region formed on the semiconductor substrate and formed at an end region of the element region;

a first semiconductor layer of a first conductivity type formed to extend in a first direction as its lengthwise direction from the element region to the element termination region, the first semiconductor layer having a first impurity concentration, the first semiconductor layer functioning as a drain region of the MOS transistor in the element region;

a third semiconductor layer of the first conductivity type formed to extend in the first direction as its lengthwise direction from the element region to the element termination region, the third semiconductor layer having a third impurity concentration that is smaller than the first impurity concentration, the third semiconductor layer being connected to the first semiconductor layer to function as a drift layer of the MOS transistor;

a field oxide film formed on a surface of the third semiconductor layer and in contact with the first semicondutor layer;

a fourth semiconductor layer of a second conductivity type formed on the semiconductor layer to extend in the first direction as its lengthwise direction from the element region to the element termination region, the fourth semiconductor layer functioning as a channel region of the MOS transistor in the element region;

a fifth semiconductor layer of the first conductivity type formed on a surface of the fourth semiconductor layer and functioning as a source region of the MOS transistor; and

a gate electrode formed on a surface of the semiconductor substrate between the third semiconductor layer and the fourth semiconductor layer, via a gate insulating film,

the element region and the element termination region having the same width along a second direction perpendicular to the first direction,

a distance between a boundary between the first semiconductor layer and the field oxide film, and the end portion of the third semiconductor layer on the side of the fifth semiconductor layer in the element region is smaller than a distance between a boundary between the first semiconductor layer and the field oxide layer and an end portion of the third semiconductor layer on the side of the fifth semiconductor layer in the element termination region.

20. The semiconductor device according to claim 19, wherein

a width of the fourth semiconductor layer along the second direction in the element termination region is smaller than a width of the fourth semiconductor layer along the second direction in the element region.