WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION

• US 20120241951A1
• Filed: 06/08/2012
• Published: 09/27/2012
• Est. Priority Date: 11/13/2009
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hu, Kunzhong (Kevin), Law, Edward
• Application Number:
  US13/492,397
• Publication Number:
  US 20120241951A1
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

Claims

1. A method of forming integrated circuit package interconnects, comprising:

receiving a wafer having a surface defined by a plurality of integrated circuit regions, each integrated circuit region having a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer; and

printing a plurality of under bump metallization (UBM) features in the form of an ink on the surface of the wafer such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals.

2. The method of claim 1, wherein said printing comprises:

printing a UBM feature in the form of an ink directly on at least one terminal of the plurality of terminals.

3. The method of claim 1, further comprising:

forming a plurality of routing interconnects on the surface of the wafer such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer;

wherein said printing comprises

printing a plurality of UBM features in the form of an ink on the plurality of routing interconnects such that each UBM feature is formed on the second portion of a respective routing interconnect of the plurality of routing interconnects.

4. The method of claim 1, further comprising:

forming a plurality of bump interconnects on the plurality of UBM features.

5. The method of claim 4, wherein said forming comprises:

printing the plurality of bump interconnects in the form of an ink on the plurality of UBM features

6. The method of claim 1, wherein the ink includes a metal paste, wherein said printing comprises:

printing the metal paste on the surface of the wafer to form the plurality of UBM features.

7. The method of claim 1, wherein said printing comprises:

ink jet printing the plurality of UBM features on the surface of the wafer.

8. The method of claim 1, wherein said printing comprises:

printing a first ink on a first region of the surface of the wafer to form a first UBM feature electrically coupled to a first terminal; and

printing a second ink on a second region of the surface of the wafer to form a second UBM feature electrically coupled to a second terminal;

wherein the second ink is different from the first ink.

9. The method of claim 1, wherein said printing comprises:

printing a plurality of layers of ink to form at least one of the UBM features.

10. The method of claim 9, wherein said printing comprises:

printing a first ink on the surface of the wafer to form a first layer of the plurality of layers of ink of a first UBM feature; and

printing a second ink on the first layer to form a second layer of the plurality of layers of ink of the first UBM feature;

wherein the second ink is different from the first ink.

11. The method of claim 1, further comprising:

singulating the wafer to form a plurality of integrated circuit packages that each include at least one integrated circuit region of the plurality of integrated circuit regions.

12. An integrated circuit package interconnect formed according to the method of claim 1.

13. A method of forming integrated circuit package interconnects, comprising:

receiving a wafer having a surface defined by a plurality of integrated circuit regions, each integrated circuit region having a passivation layer and at least one terminal on the surface of the wafer accessible through an opening in the passivation layer; and

ink jet printing at least one under bump metallization (UBM) feature in the form of a nanopaste on the surface of the wafer such that the at least one UBM feature is formed electrically coupled with the at least one terminal.

14. The method of claim 13, wherein said printing comprises:

printing at least one UBM feature in the form of a nanopaste directly on the at least one terminal.

15. The method of claim 13, further comprising:

forming at least one routing interconnect on the surface of the wafer such that the at least one routing interconnect has a first portion in contact with the at least one terminal and has a second portion that extends over the passivation layer;

wherein said printing comprises

printing at least one UBM feature in the form of a nanopaste on the at least one routing interconnect such that the at least one UBM feature is formed on the second portion of the at least one routing interconnect.

16. An integrated circuit package interconnect formed according to the method of claim 13.

20. An integrated circuit package formed according to the method of claim 13.

17. A method of forming integrated circuit packages, comprising:

receiving a wafer having a surface defined by a plurality of integrated circuit regions, each integrated circuit region having a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer;

printing a plurality of under bump metallization (UBM) features in the form of an ink on the surface of the wafer such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals;

forming a plurality of bump interconnects on the plurality of UBM features; and

singulating the wafer to form a plurality of integrated circuit packages that each include at least one integrated circuit region of the plurality of integrated circuit regions

18. The method of claim 17, wherein the plurality of bump interconnects is arranged in an array of bump interconnects.

19. The method of claim 17, further comprising:

forming a plurality of routing interconnects on the surface of the wafer such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer;

wherein said printing comprises

printing a plurality of UBM features in the form of an ink on the plurality of routing interconnects such that each UBM feature is formed on the second portion of a respective routing interconnect of the plurality of routing interconnects.