CHIP SCALE PACKAGE ASSEMBLY IN RECONSTITUTION PANEL PROCESS FORMAT

• US 20120241955A1
• Filed: 03/25/2011
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Law, Edward, Khan, Rezaur R., Law, Edmund
• Granted Patent: US 8,367,475 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.

Claims

1. A method, comprising:

forming a substrate panel that includes a plurality of substrates that each include routing;

testing the substrates in the substrate panel to determine a set of working substrates;

singulating the substrate panel to separate the plurality of substrates;

attaching a subset of the separated substrates to a surface of a carrier, the subset of the separated substrates being the set of working substrates;

mounting one or more dies to each of the substrates on the carrier;

encapsulating the dies and the substrates on the carrier with a molding compound;

detaching the carrier from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates;

attaching a plurality of interconnects to each of the substrates at a surface of the molded assembly; and

singulating the molded assembly to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the dies and a substrate having a peripheral ring of the molding compound around an outer edge of the substrate.

2. The method of claim 1, further comprising:

plating the substrates in the substrate panel with studs to form conductive contacts for mounting the dies to the substrates.

3. The method of claim 1, wherein said forming a substrate panel that includes a plurality of substrates that each include routing comprises:

forming the substrate panel to include the substrates in an array that fills the substrate panel except for a perimeter rim area of the substrate panel around the array.

4. The method of claim 1, wherein said attaching a subset of the separated substrates to a surface of a carrier comprises:

positioning the separated substrates to be spaced apart on the surface of the carrier.

5. The method of claim 4, wherein said encapsulating the dies and the substrates on the carrier with a molding compound comprises:

filling a space between the separated substrates with the molding compound.

6. The method of claim 5, wherein said singulating the molded assembly to form a plurality of integrated circuit packages comprises:

singulating the molded assembly so that each integrated circuit package includes a peripheral ring of molding compound around an outer edge of the included substrate.

7. The method of claim 1, wherein the interconnects are ball interconnects.

19. An integrated circuit package assembled according to the method of claim 1.

8. (canceled)

9. A method, comprising:

receiving a plurality of separate substrates singulated from a substrate panel and tested to be working substrates;

attaching the substrates to a surface of a carrier;

mounting one or more dies to each of the substrates on the carrier;

encapsulating the dies and the substrates on the carrier with a molding compound;

detaching the carrier from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates;

attaching a plurality of interconnects to each of the substrates at a surface of the molded assembly; and

singulating the molded assembly to form a plurality of integrated circuit packages, each integrated circuit package including at least one of the dies and a substrate having a peripheral ring of the molding compound around an outer edge of the substrate.

10. The method of claim 9, wherein said attaching the substrates to a surface of a carrier comprises:

positioning the substrates to be spaced apart on the surface of the carrier.

11. The method of claim 10, wherein said encapsulating the dies and the substrates on the carrier with a molding compound comprises:

filling a space between the substrates with the molding compound.

12. The method of claim 11, wherein said singulating the molded assembly to form a plurality of integrated circuit packages comprises:

singulating the molded assembly so that each integrated circuit package includes a peripheral ring of molding compound around an outer edge of the included substrate.

13. The method of claim 9, wherein the interconnects are ball interconnects.

20. An integrated circuit package assembled according to the method of claim 9.

14. (canceled)

15. An integrated circuit package, comprising:

a substrate that has opposing first and second surfaces;

a die mounted to the first surface of the substrate; and

molding compound that encapsulates the die on the first surface of the substrate and forms a peripheral ring around an outer edge of the substrate, the peripheral ring of molding compound remaining from saw singulation of the integrated circuit package from a molded assembly and covering the outer edge of the substrate entirely.

16. The package of claim 15, wherein the plurality of interconnects comprises:

a plurality of interconnect balls attached to the second surface of the substrate.

17. The package of claim 15, further comprising:

a plurality of studs that couple terminals of the die to conductive features on the first surface of the substrate.

18. The package of claim 15, further comprising:

a plurality of solder bumps that couple terminals of the die to conductive features on the first surface of the substrate.

21. The package of claim 15, wherein the substrate is determined to be a working substrate during testing of the substrate in a substrate panel prior to singulation from the substrate panel.

22. The package of claim 15, wherein the substrate includes at least one electrically insulating layer and a plurality of electrically conductive layers, each of the electrically conductive layers including a plurality of electrically conductive features.