Pin Routing in Standard Cells

• US 20120241986A1
• Filed: 03/23/2011
• Published: 09/27/2012
• Est. Priority Date: 03/23/2011
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Sherlekar, Deepak D., Hovsepyan, Vahe
• Granted Patent: US 8,612,914 B2
• Time in Patent Office: Days
• US Class Current: 257/784
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Cells designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid. The cells includes cell pins that are located within the cell based on the offsets of the routing tracks relative to the cell boundaries. The cell pins are wider than wires that are routed along the metal routing tracks. The standard cell may be placed in a layout in either a normal orientation or in a flipped orientation. In both orientations, the cell pins are aligned with the wires that are routed along the metal routing tracks.

Claims

1. An integrated circuit comprising:

a first metal wire extending along a first routing track that is parallel to an axis, the first metal wire having a first width that is equal to a minimum metal width for metal wires defined by a design rule;

a second metal wire extending along a second routing track that is parallel to the axis, the second metal wire having a width that is equal to the first width, the first routing track and the second routing track separated by one or more routing pitches, wherein the routing pitch is an odd multiple of a manufacturing grid;

a first cell instance including a plurality of cell pins, the cell pins including a first cell pin that is connected to the first metal wire, wherein the first cell pin extends in a first direction from the first routing track by at least half the first width and extends in a second direction from the first routing track by more than half the first width; and

a second cell instance which is a flipped version of the first cell instance relative to the axis, the second cell instance including a second pin corresponding to the first pin and connected to the second metal wire.

2. The integrated circuit of claim 1, wherein the first routing track is offset from a boundary of the cell by a distance corresponding to zero or more routing pitches plus one of:

floor of half the routing pitch or ceiling of half the routing pitch.

3. The integrated circuit of claim 1, wherein the second cell pin extends in the first direction from the second routing track by at least half the first width and extends in the second direction from the second routing track by more than half the first width.

4. An integrated circuit comprising:

a first metal wire extending along a first routing track that is parallel to an axis, the first metal wire having a width that is equal to a first width;

a second metal wire extending along a second routing track that is parallel to the axis, the second metal wire having a width that is equal to the first width, the first routing track and the second routing track separated by one or more routing pitches;

a first cell instance including a plurality of cell pins, the cell pins including a first cell pin that is connected to the first metal wire, the first cell pin having a second width that is greater than the first width; and

a second cell instance which is a flipped version of the first cell instance relative to the axis, the second cell instance including a second pin corresponding to the first pin and connected to the second metal wire.

5. The integrated circuit of claim 4, wherein the routing pitch is an odd multiple of a manufacturing grid, the manufacturing grid defining a grid to which objects in the integrated circuit are aligned.

6. The integrated circuit of claim 5, wherein the first routing track is offset from a boundary of the first cell instance by a distance corresponding to zero or more routing pitches plus one of:

floor of half the routing pitch or ceiling of half the routing pitch.

7. The integrated circuit of claim 6, wherein the first width corresponds to a minimum width for metal wires defined by a restrictive design rule.

8. The integrated circuit of claim 4, wherein the first cell pin extends in a first direction from the first routing track by at least half the first width and extends in a second direction from the first routing track by more than half the first width.

9. The integrated circuit of claim 8, wherein the second cell pin extends in the first direction from the second routing track by at least half the first width and extends in the second direction from the second routing track by more than half the first width.

10. The integrated circuit of claim 4, wherein the first cell instance comprises a plurality of gates that are parallel to the axis, the gates having a pitch that is equal to the routing pitch.

11. The integrated circuit of claim 4, wherein the first metal wire is centered on the first routing track and the second metal wire is centered on the second routing track.

12. The integrated circuit of claim 4, wherein the first metal wire, second metal wire, first cell pin, and second cell pin are in a common metal layer.

13. A computer-implemented method comprising:

receiving a cell library including a plurality of cells; and

generating a layout for an integrated circuit by arranging instances of the cells, the layout comprising;

a first metal wire extending along a first routing track that is parallel to an axis, the first metal wire having a width that is equal to a first width;

a second metal wire extending along a second routing track that is parallel to the axis, the second metal wire having a width that is equal to the first width, the first routing track and the second routing track separated by one or more routing pitches;

a first cell instance including a plurality of cell pins, the cell pins including a first cell pin that is connected to the first metal wire, the first cell pin having a second width that is greater than the first width; and

a second cell instance which is a flipped version of the first cell instance relative to the axis, the second cell including a second pin corresponding to the first pin and connected to the second metal wire.

14. The method of claim 13, wherein the routing pitch is an odd multiple of a manufacturing grid, the manufacturing grid defining a grid to which objects in the layout are aligned.

15. The method of claim 14, wherein the first routing track is offset from a boundary of the first cell instance by a distance corresponding to zero or more routing pitches plus one of:

floor of half the routing pitch or ceiling of half the routing pitch.

16. The method of claim 15, wherein the first width corresponds to a minimum width for metal wires defined by a restrictive design rule.

17. The method of claim 13, wherein the first cell pin extends in a first direction from the first routing track by at least half the first width and extends in a second direction from the first routing track by more than half the first width.

18. The method of claim 17, wherein the second cell pin extends in the first direction from the second routing track by at least half the first width and extends in the second direction from the second routing track by more than half the first width.

19. A system for generating a layout of an integrated circuit, the system comprising:

a processor; and

a non-transitory computer readable medium storing instructions, the instructions when executed by the processor cause the processor to;

receive a cell library including a plurality of cells; and

generate a layout for an integrated circuit by arranging instances of the cells, the layout comprising;

a first metal wire extending along a first routing track that is parallel to an axis, the first metal wire having a width that is equal to a first width;

a second metal wire extending along a second routing track that is parallel to the axis, the second metal wire having a width that is equal to the first width, the first routing track and the second routing track separated by one or more routing pitches;

a first cell instance including a plurality of cell pins, the cell pins including a first cell pin that is connected to the first metal wire, the first cell pin having a second width that is greater than the first width; and

a second cell instance which is a flipped version of the first cell instance relative to the axis, the second cell instance including a second pin corresponding to the first pin and connected to the second metal wire.

20. The system of claim 19, wherein the routing pitch is an odd multiple of a manufacturing grid, the manufacturing grid defining a grid to which objects in the layout are aligned.

21. The system of claim 20, wherein the first routing track is offset from a boundary of the first cell instance by a distance corresponding to zero or more routing pitches plus one of:

floor of half the routing pitch or ceiling of half the routing pitch.

22. The system of claim 21, wherein the first width corresponds to a minimum width for metal wires defined by a restrictive design rule.

23. The system of claim 19, wherein the first cell pin extends in a first direction from the first routing track by at least half the first width and extends in a second direction from the first routing track by more than half the first width.

24. The system of claim 23, wherein the second cell pin extends in the first direction from the second routing track by at least half the first width and extends in the second direction from the second routing track by more than half the first width.

25. A non-transitory computer readable medium structured to store instructions executable by a processor, the instructions when executed cause the processor to:

receive a cell library including a plurality of cells; and

generate a layout for an integrated circuit by arranging instances of the cells, the layout comprising;

a first metal wire extending along a first routing track that is parallel to an axis, the first metal wire having a width that is equal to a first width;

a second metal wire extending along a second routing track that is parallel to the axis, the second metal wire having a width that is equal to the first width, the first routing track and the second routing track separated by one or more routing pitches;

a first cell instance including a plurality of cell pins, the cell pins including a first cell pin that is connected to the first metal wire, the first cell pin having a second width that is greater than the first width; and

a second cell instance which is a flipped version of the first cell instance relative to the axis, the second cell including a second pin corresponding to the first pin and connected to the second metal wire.