RESISTANCE CHANGE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120243307A1
• Filed: 03/19/2012
• Published: 09/27/2012
• Est. Priority Date: 03/23/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takashima, Daisaburo
• Granted Patent: US 9,025,369 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and drains connected in series is connected to a source of the select transistor. The bit line is connected a drain of the select transistor. The memory cell array is obtained by forming a memory cell string.

Claims

1. A phase change memory comprising:

a memory cell comprising a chalcogenide wiring, resistance wirings, which becomes a heater, of which each of one end is connected to each of both ends of the chalcogenide wiring, and a cell transistor to a source and a drain of which the other ends of resistance wirings are connected;

a block select transistor to a source of which one end of a plurality of memory cells with sources and drains connected in series is connected and to a drain of which a bit line is connected; and

a memory cell array obtained by forming the memory cell strings by connecting the other end of the memory cells connected in series to a source line, connecting a gate of the memory cell to a word line, and connecting a gate of the block select transistor to a block select line, and by arranging a plurality of memory cell strings.

4. The memory according to claim 1, wherein

the chalcogenide wiring is formed on a gate of the cell transistor through an insulating film, and

a direction in which the both ends of the chalcogenide wiring are connected is parallel to a wiring direction of the bit line.

7. The memory according to claim 4, wherein

a direction in which the both ends of the resistance wiring, which becomes the heater is connected, is perpendicular to the wiring direction of the bit line.

9. The memory according to claim 1, wherein

the chalcogenide wiring is formed after a resistance element, which becomes the heater, is formed on a side wall of a gate of the cell transistor.

10. The memory according to claim 1, wherein the chalcogenide wiring is formed on the gate of the cell transistor, and thereafter a resistance element, which becomes the heater, is formed on a side wall of the gate of the cell transistor.

11. The memory according to claim 1, wherein

resistance of the chalcogenide wiring is stored as 2 to the power of N (N is a natural number not smaller than 1) types and N bits are stored in the chalcogenide wiring.

12. The memory according to claim 1, wherein

at read operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby providing potential difference between the source line and the bit line to read cell data by difference in a current, which flows to the memory cell.

14. The memory according to claim 1, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby differentiating an amount of current, which flows between the source line and the bit line, and time during which the current is applied to realize transition to an amorphous state and a crystal state of the chalcogenide wiring of the selected memory cell.

17. The memory according to claim 9, wherein

at read operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby providing potential difference between the source line and the bit line to read cell data by difference in a current, which flows to the memory cell.

19. The memory according to claim 9, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby differentiating an amount of current, which flows between the source line and the bit line, to realize transition to low resistance and high resistance of a resistance change material of the selected memory cell.

21. The memory according to claim 9, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby changing a polarity of a current, which flows between the source line and the bit line, to realize transition to low resistance and high resistance of the resistance change material of the selected memory cell.

2. A phase change memory comprising:

a memory cell comprising a chalcogenide wiring and a cell transistor to a source and a drain of which both ends of the chalcogenide wiring are connected;

a block select transistor to a source of which one end of a plurality of memory cells with sources and drains connected in series is connected and to a drain of which a bit line is connected; and

a memory cell array obtained by forming a memory cell string by connecting the other end of the memory cells connected in series to a source line, connecting a gate of the memory cell to a word line, and connecting a gate of the block select transistor to a block select line, and by arranging a plurality of memory cell strings.

5. The memory according to claim 2, wherein

the chalcogenide wiring is formed on a gate of the cell transistor through an insulating film, and

a direction in which the both ends of the chalcogenide wiring are connected is parallel to a wiring direction of the bit line.

13. The memory according to claim 2, wherein

at read operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby providing potential difference between the source line and the bit line to read cell data by difference in a current, which flows to the memory cell.

15. The memory according to claim 2, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby differentiating an amount of current, which flows between the source line and the bit line, and time during which the current is applied to realize transition to an amorphous state and a crystal state of the chalcogenide wiring of the selected memory cell.

3. A resistance change memory comprising:

a memory cell comprising a resistance change material wiring, first and second metal wirings one ends of which are connected to both ends of the resistance change material wiring, respectively, and a cell transistor to a source of which the other end of the first metal wiring is connected and to a drain of which the other end of the second metal wiring is connected;

a block select transistor to a source of which one end of a plurality of memory cells with sources and drains connected in series is connected and to a drain of which a bit line is connected; and

a memory cell array obtained by forming a memory cell string by connecting the other end of the memory cells connected in series to a source line, connecting a gate of the memory cell to a word line, and connecting a gate of the block select transistor to a block select line, and by arranging a plurality of memory cell strings.

6. The memory according to claim 3, wherein

the resistance change material wiring is formed on a gate of the cell transistor through an insulating film, and

a direction in which the both ends of the resistance change material wiring is connected is parallel to a wiring direction of the bit line.

8. The memory according to claim 6, wherein

a direction in which the both ends of the first metal wiring are connected is perpendicular to the wiring direction of the bit line.

16. The memory according to claim 3, wherein

at read operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby providing potential difference between the source line and the bit line to read cell data by difference in a current, which flows to the memory cell.

18. The memory according to claim 3, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby differentiating an amount of current, which flows between the source line and the bit line, to realize transition to low resistance and high resistance of a resistance change material of the selected memory cell.

20. The memory according to claim 3, wherein

at write operation time, the word line connected to a selected cell of a selected memory cell string is set to LOW, the word line connected to a non-selected cell of the selected memory cell string is set to HIGH, and the block select line of the selected memory cell string is set to HIGH, thereby changing a polarity of a current, which flows between the source line and the bit line, to realize transition to low resistance and high resistance of the resistance change material of the selected memory cell.