NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120243314A1
• Filed: 11/22/2011
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEDA, Takashi
• Granted Patent: US 8,488,378 B2
• Time in Patent Office: Days
• US Class Current: 365/185.05
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a memory string having a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate;

a plurality of first conductive layers electrically connected to gates of the memory cells;

a second conductive layer electrically connected to a gate of the dummy transistor; and

a third conductive layer electrically connected to a gate of the back gate transistor,

the second conductive layer being short-circuited with the third conductive layer.

2. The nonvolatile semiconductor memory device according to claim 1, wherein a pair of dummy transistors is provided in the memory string,

a pair of second conductive layers is correspondingly provided in the same layer as the pair of dummy transistors, and

at least one of the pair of second conductive layers is short-circuited with the third conductive layer.

3. The nonvolatile semiconductor memory device according to claim 2, wherein the pair of second conductive layers is short-circuited with the third conductive layer.

4. The nonvolatile semiconductor memory device according to claim 1, wherein two pairs of dummy transistors are provided in the memory string,

one pair of the second conductive layers is provided in a first layer for one pair of dummy transistors and another pair of the second conductive layers is provided in a second layer different from the first layer for another pair of dummy transistors, and

at least one of the two pairs of the second conductive layers is short-circuited with the third conductive layer.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the second conductive layer is provided above the plurality of first conductive layers.

6. The nonvolatile semiconductor memory device according to claim 1, further comprising:

an upper wiring layer provided above the first conductive layers and the second conductive layer, and extending in parallel to the semiconductor substrate,

a first plug layers electrically connects the second conductive layer and the upper wiring layer; and

a second plug layers electrically connects the third conductive layer and the upper wiring layer.

7. The nonvolatile semiconductor memory device according to claim 6, comprising:

a columnar semiconductor layer extending in a direction perpendicular to the semiconductor substrate,

wherein the columnar semiconductor layer has a diameter of a first length,

the first conductive layers and the second conductive layer each comprise a plurality of meshing parts each having a width of a second length twice the first length in a first direction parallel to the semiconductor substrate, and arranged at an interval of the first length in the first direction, and

the upper wiring layers each have a width of the first length in the first direction and are arranged at an interval of the first length in the first direction.

8. The nonvolatile semiconductor memory device according to claim 1, wherein the memory string comprises:

a pair of columnar semiconductor layers extending in a direction perpendicular to the semiconductor substrate and functioning as bodies of the memory cells and a body of the dummy transistor;

a joining semiconductor layer joining lower ends of the pair of columnar semiconductor layers and functioning as a body of the back gate transistor; and

a charge storage layer formed to surround the columnar semiconductor layers and the joining semiconductor layer,

the plurality of first conductive layers are formed to surround the columnar semiconductor layers via the charge storage layer,

the second conductive layer is formed to surround the columnar semiconductor layers via the charge storage layer, and

the third conductive layer is formed to surround the joining semiconductor layer via the charge storage layer.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the first conductive layers are formed stepwise such that ends of the first conductive layers are located at different positions in a first direction parallel to the semiconductor substrate.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the first conductive layers, the second conductive layer and the third conductive layer include polysilicon.

11. The nonvolatile semiconductor memory device according to claim 10, wherein the columnar semiconductor layers and the joining semiconductor layer include polysilicon.

12. The nonvolatile semiconductor memory device according to claim 8, wherein the charge storage layer includes silicon nitride.

13. The nonvolatile semiconductor memory device according to claim 8, further comprising a block insulative layer provided between the charge storage layer, and the first conductive layers, the second conductive layer and the third conductive layer,

wherein the block insulative layer includes silicon oxide.

14. The nonvolatile semiconductor memory device according to claim 8, further comprising a tunnel insulative layer provided between the charge storage layer, and the columnar semiconductor layer and the joining semiconductor layer,

wherein the tunnel insulative layer includes silicon oxide.

15. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a first select transistor connected at one end to one end of the memory string;

a second select transistor connected at one end to the other end of the memory string; and

a control circuit configured to control a voltage to be given to the memory cells, the dummy transistor, the back gate transistor, the first select transistor and the second select transistor.

16. The nonvolatile semiconductor memory device according to claim 15, wherein, in an erase operation erasing data held by the memory cells, the control circuit generates a GIDL current by a potential difference between a gate of the first select transistor and the other end of the first select transistor, thereby increasing a potential of bodies of the memory cells.

17. The nonvolatile semiconductor memory device according to claim 16, wherein, in the erase operation, the control circuit generates a GIDL current by a potential difference between a gate of the second select transistor and the other end of the second select transistor, thereby increasing a potential of bodies of the memory cells.

18. The nonvolatile semiconductor memory device according to claim 16, wherein a plurality of memory strings are arranged in a matrix in a first direction parallel to the semiconductor substrate and in a second direction perpendicular to the first direction,

gates of a plurality of first select transistors arranged in the first direction are commonly connected,

gates of a plurality of second select transistors arranged in the first direction are commonly connected, and

the control circuit selectively performs the erase operation to the memory cells arranged in the first direction.

19. The nonvolatile semiconductor memory device according to claim 6, wherein

the number of the plurality of first conductive layers in each of memory blocks is N,

the number of the plurality of memory strings arranged in a first direction parallel to the semiconductor substrate in each of the memory blocks is M,

the upper plug layers are provided at a pitch of 2F in the first direction, and

N, M, and F satisfy a following equation.

6F×

M≧

2F×

(N+M)

20. The nonvolatile semiconductor memory device according to claim 1, wherein the third conductive layer is provided below the plurality of first conductive layers.