MEMORY SYSTEM

• US 20120243329A1
• Filed: 09/22/2011
• Published: 09/27/2012
• Est. Priority Date: 03/25/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NAGASHIMA, Hiroyuki
• Granted Patent: US 8,755,233 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

Claims

1. A memory system comprising:

a non-volatile memory device which stores data;

a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and

a changing unit which changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value, the writing process being a process in which a writing operation and a verification operation are alternately repeated.

2. The memory system according to claim 1, wherein

the monitored characteristic of the non-volatile memory device includes at least one of a frequency of the writing process, a frequency of the erasing process, a time necessary for the writing process, a time necessary for the erasing process, a repeat count of the writing operation and the verification operation in the writing process, and a repeat count of an erasing operation and a verification operation in the erasing process.

3. The memory system according to claim 1, wherein

the changing unit gradually changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process, in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

4. The memory system according to claim 3,

wherein the monitoring unit determines a variation in the monitored characteristic of the non-volatile memory device step by step, and

wherein the changing unit gradually changes at least a value of an erasing start voltage in the erasing process in accordance with a result determined by the monitoring unit so that a time necessary for the erasing process is equal to or less than the target value.

5. The memory system according to claim 1, wherein

the changing unit continuously changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

6. The memory system according to claim 5, wherein

the changing unit includes:

a calculation unit which calculates a change amount of at least one of the value of the writing start voltage and the increase width of the writing voltage in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value, and

a changing processing unit which changes at least one of the value of the writing start voltage and the increase width of the writing voltage in the writing process by means of the calculated change amount.

7. The memory system according to claim 1, wherein

the changing unit changes the value of the writing start voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

8. The memory system according to claim 1, wherein

the changing unit changes the increase width of the writing voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

9. The memory system according to claim 1, wherein

the changing unit changes both the value of the writing start voltage and the increase width of the writing voltage in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

10. The memory system according to claim 1, wherein

the changing unit further changes a verification voltage in the writing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

11. A memory system comprising:

a non-volatile memory device which stores data;

a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and

a changing unit which changes at least a value of an erasing start voltage in the erasing process in accordance with the monitored characteristic so that a time necessary for the erasing process is equal to or less than a target value.

12. The memory system according to claim 11, wherein

the changing unit gradually changes at least the value of the erasing start voltage in the erasing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the erasing process is equal to or less than the target value.

13. The memory system according to claim 12,

wherein the monitoring unit determines a variation in the monitored characteristic of the non-volatile memory device, and

wherein the changing unit gradually changes at least the value of the erasing start voltage in the erasing process, based on a result determined by the monitoring unit so that the time necessary for the erasing process is equal to or less than the target value.

14. The memory system according to claim 11, wherein

the changing unit changes both the value of the erasing start voltage and the increase width of the erasing voltage in the erasing process in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the erasing process is equal to or less than the target value.

15. A memory system comprising:

a non-volatile memory device which stores data;

a monitoring unit which monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device; and

a changing unit which changes a type of verification operation in the writing process from a first type of verification operation to a second type of verification operation in accordance with the monitored characteristic, the writing process being a process in which a writing operation and a verification operation are alternately repeated, the first type of verification operation being a operation where a verification is performed at a second verification voltage, the second type of verification operation being a operation where a verification is performed in two steps at a first verification voltage and at the second verification voltage, the first verification voltage being lower than the second verification voltage.

16. The memory system according to claim 15, wherein

the changing unit changes at least one of a level of the first verification voltage and a charging voltage of a bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

17. The memory system according to claim 16, wherein

the changing unit gradually changes at least one of the level of the first verification voltage and the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

18. The memory system according to claim 16, wherein

the changing unit changes the level of the first verification voltage in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

19. The memory system according to claim 16, wherein

the changing unit changes the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.

20. The memory system according to claim 16, wherein

the changing unit changes both the level of the first verification voltage and the charging voltage of the bit line in the second type of verification operation in accordance with the monitored characteristic of the non-volatile memory device so that the time necessary for the writing process is substantially identical to the target value.